From nobody Sun Feb 8 01:31:15 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 987E32D061D for ; Fri, 19 Dec 2025 12:26:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766147198; cv=none; b=gi4vzPqOdlFSwn1AaFfOXEHAdrEFeuLJAFK+VUFJi7Y2B4bS0TEIHUFb008kuj22OqZLgA7X4vJ6vWmPDhZoRCUMxwKUdrFPYKVMRH7ezLkX+fIbMPAhbfAvI+uQ5hgIfLt/uLu2G053urHVR45KySTCNdBOUSOi19Bi6gyq8l8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1766147198; c=relaxed/simple; bh=wagqnRdTBbUsILMcJf1f32B9TXZEuDlygQkfjd+mIOM=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=E4xLvpTYPid6bCCJNGq+Wl6ADm6DK5WdOoeZUHBIIsJEVIFo8nWEqyjbvhMsq+XGUwsVFSpsyqvIEJrw6QpDiTJsz+stwz6kHNlkPdLgLRUFC+zb7MHHndoM0/lXXgOmdzFtmOxHyJMIku5HgVbJpFFH8QThk93xakptnPJwTYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=W409ey83; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="W409ey83" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8C3E2C4CEF1; Fri, 19 Dec 2025 12:26:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1766147198; bh=wagqnRdTBbUsILMcJf1f32B9TXZEuDlygQkfjd+mIOM=; h=From:To:Cc:Subject:Date:From; b=W409ey83NSYeygetEDHGgW3gRH8uE5k8Ba/ue8GfL4NYzoiMyuaxmoFNZcJsWfnS5 GyIGgQj+ptkHkcQVnxe4Ss7BL4laJ568Cw4wnzjiBVZUh/i71tzf8e5ln4W6XLDP6y 7FF40QCkIvCcy1+r1GX0pupDSJoNzuGAw8cXZmF6bRoqLyuBgtpCrQ58Jl6FibRtSf vJRpaBW7ZA/aAEXPA2MyMxc6Q3kfMkBpsi43zxqJEmDST8hD3KN0w0CDuo2zrOpnIa WtY1eEoqmqCj8ZWXtMOnczIhYstLYg2aUHRmZB1uAcEivC/MWUpb8m0g7wK486cw1O 5ktrGe3aTTn6Q== From: "Christophe Leroy (CS GROUP)" To: Michael Ellerman , Nicholas Piggin , Madhavan Srinivasan Cc: "Christophe Leroy (CS GROUP)" , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, Christian Zigotzky , Guenter Roeck Subject: [PATCH] powerpc/32: Restore disabling of interrupts at interrupt/syscall exit Date: Fri, 19 Dec 2025 13:23:52 +0100 Message-ID: <585ea521b2be99d293b539bbfae148366cfb3687.1766146895.git.chleroy@kernel.org> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4242; i=chleroy@kernel.org; h=from:subject:message-id; bh=wagqnRdTBbUsILMcJf1f32B9TXZEuDlygQkfjd+mIOM=; b=owGbwMvMwCV2d0KB2p7V54MZT6slMWS6Ot/Qb1SozrXRP7G98tXMpdbl2xmZC2s/d4eXT2AMn xdjdNC0o5SFQYyLQVZMkeX4f+5dM7q+pOZP3aUPM4eVCWQIAxenAEwkMJGR4dXBDW82ZiwVklBs +KlUI8Vi3Lx0zyT10t+T7Z4teMPwlp3hD2/q3xtdd3ZcNmN1fWpyM5F7hTlbu1vCeVttT4vzDt5 SHAA= X-Developer-Key: i=chleroy@kernel.org; a=openpgp; fpr=10FFE6F8B390DE17ACC2632368A92FEB01B8DD78 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 2997876c4a1a ("powerpc/32: Restore clearing of MSR[RI] at interrupt/syscall exit") delayed clearing of MSR[RI], but missed that both MSR[RI] and MSR[EE] are cleared at the same time, so the commit also delayed the disabling of interrupts, leading to unexpected behaviour. To fix that, mostly revert the blamed commit and restore the clearing of MSR[RI] in interrupt_exit_kernel_prepare() instead. For 8xx it implies adding a synchronising instruction after the mtspr in order to make sure no instruction counter interrupt (used for perf events) will fire just after clearing MSR[RI]. Reported-by: Christian Zigotzky Closes: https://lore.kernel.org/all/4d0bd05d-6158-1323-3509-744d3fbe8fc7@xe= nosoft.de/ Reported-by: Guenter Roeck Closes: https://lore.kernel.org/all/6b05eb1c-fdef-44e0-91a7-8286825e68f1@ro= eck-us.net/ Fixes: 2997876c4a1a ("powerpc/32: Restore clearing of MSR[RI] at interrupt/= syscall exit") Signed-off-by: Christophe Leroy (CS GROUP) Tested-by Christian Zigotzky Tested-by: Christian Zigotzky --- arch/powerpc/include/asm/hw_irq.h | 2 +- arch/powerpc/include/asm/reg.h | 1 + arch/powerpc/kernel/entry_32.S | 15 --------------- arch/powerpc/kernel/interrupt.c | 5 ++++- 4 files changed, 6 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/h= w_irq.h index 1078ba88efaf..9cd945f2acaf 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -90,7 +90,7 @@ static inline void __hard_EE_RI_disable(void) if (IS_ENABLED(CONFIG_BOOKE)) wrtee(0); else if (IS_ENABLED(CONFIG_PPC_8xx)) - wrtspr(SPRN_NRI); + wrtspr_sync(SPRN_NRI); else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64)) __mtmsrd(0, 1); else diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 3fe186635432..3449dd2b577d 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1400,6 +1400,7 @@ static inline void mtmsr_isync(unsigned long val) : "r" ((unsigned long)(v)) \ : "memory") #define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",2" : : : "memor= y") +#define wrtspr_sync(rn) asm volatile("mtspr " __stringify(rn) ",2; sync" := : : "memory") =20 static inline void wrtee(unsigned long val) { diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S index 16f8ee6cb2cd..d8426251b1cd 100644 --- a/arch/powerpc/kernel/entry_32.S +++ b/arch/powerpc/kernel/entry_32.S @@ -101,17 +101,6 @@ SYM_FUNC_END(__kuep_unlock) .endm #endif =20 -.macro clr_ri trash -#ifndef CONFIG_BOOKE -#ifdef CONFIG_PPC_8xx - mtspr SPRN_NRI, \trash -#else - li \trash, MSR_KERNEL & ~MSR_RI - mtmsr \trash -#endif -#endif -.endm - .globl transfer_to_syscall transfer_to_syscall: stw r3, ORIG_GPR3(r1) @@ -160,7 +149,6 @@ ret_from_syscall: cmpwi r3,0 REST_GPR(3, r1) syscall_exit_finish: - clr_ri r4 mtspr SPRN_SRR0,r7 mtspr SPRN_SRR1,r8 =20 @@ -237,7 +225,6 @@ fast_exception_return: /* Clear the exception marker on the stack to avoid confusing stacktrace = */ li r10, 0 stw r10, 8(r11) - clr_ri r10 mtspr SPRN_SRR1,r9 mtspr SPRN_SRR0,r12 REST_GPR(9, r11) @@ -270,7 +257,6 @@ interrupt_return: .Lfast_user_interrupt_return: lwz r11,_NIP(r1) lwz r12,_MSR(r1) - clr_ri r4 mtspr SPRN_SRR0,r11 mtspr SPRN_SRR1,r12 =20 @@ -313,7 +299,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX) cmpwi cr1,r3,0 lwz r11,_NIP(r1) lwz r12,_MSR(r1) - clr_ri r4 mtspr SPRN_SRR0,r11 mtspr SPRN_SRR1,r12 =20 diff --git a/arch/powerpc/kernel/interrupt.c b/arch/powerpc/kernel/interrup= t.c index aea6f7e8e9c6..e63bfde13e03 100644 --- a/arch/powerpc/kernel/interrupt.c +++ b/arch/powerpc/kernel/interrupt.c @@ -38,7 +38,7 @@ static inline bool exit_must_hard_disable(void) #else static inline bool exit_must_hard_disable(void) { - return false; + return true; } #endif =20 @@ -443,6 +443,9 @@ notrace unsigned long interrupt_exit_kernel_prepare(str= uct pt_regs *regs) =20 if (unlikely(stack_store)) __hard_EE_RI_disable(); +#else + } else { + __hard_EE_RI_disable(); #endif /* CONFIG_PPC64 */ } =20 --=20 2.49.0