From nobody Mon Feb 9 20:36:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1298C0015E for ; Tue, 25 Jul 2023 22:24:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232869AbjGYWYm (ORCPT ); Tue, 25 Jul 2023 18:24:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232747AbjGYWWp (ORCPT ); Tue, 25 Jul 2023 18:22:45 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8747A4EDD; Tue, 25 Jul 2023 15:17:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690323477; x=1721859477; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TDllGKwd/erLe7EXvszdxaN+tTcjl339wwIEld81mrM=; b=L7RkXrJwjsqlzbSUoTR1qlaXN+ehIgifRVWAVO4+JUeUq7PedP8KC2mr kZFGCZMeer7vx3hWKdQ0YxSMTX08AGnaDi/EWIdvl4aOYGe4Oxfy/Ytf4 PCJ7zrJ/2luU75WQYQOnAcf6O7GuJrnoB+KCMlFXmbUzpaxSCKVrfRWl4 2Pa3gBpsH8X7fhefwS7QrqQmRsNii7s1xN8QhQelZKtrgY3Z7tpjHuuME lOD6bJe6iwQm/wG7nEKMHU9iosTq9RbEjilMia2YwA7DKUkrzCxGP7kde epEubidz0AktvhkKsKK/H+RfNj+BfqDWR3W15MD+pCxkvnKstvN31W8jU g==; X-IronPort-AV: E=McAfee;i="6600,9927,10782"; a="367882681" X-IronPort-AV: E=Sophos;i="6.01,231,1684825200"; d="scan'208";a="367882681" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2023 15:16:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10782"; a="840001883" X-IronPort-AV: E=Sophos;i="6.01,231,1684825200"; d="scan'208";a="840001883" Received: from ls.sc.intel.com (HELO localhost) ([172.25.112.31]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2023 15:16:01 -0700 From: isaku.yamahata@intel.com To: kvm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: isaku.yamahata@intel.com, isaku.yamahata@gmail.com, Paolo Bonzini , erdemaktas@google.com, Sean Christopherson , Sagi Shahar , David Matlack , Kai Huang , Zhi Wang , chen.bo@intel.com, hang.yuan@intel.com, tina.zhang@intel.com Subject: [PATCH v15 088/115] KVM: TDX: Handle EXIT_REASON_OTHER_SMI with MSMI Date: Tue, 25 Jul 2023 15:14:39 -0700 Message-Id: <5658a07b6e119070190886d056a35a8f0e660539.1690322424.git.isaku.yamahata@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Isaku Yamahata When BIOS eMCA MCE-SMI morphing is enabled, the #MC is morphed to MSMI (Machine Check System Management Interrupt). Then the SMI causes TD exit with the read reason of EXIT_REASON_OTHER_SMI with MSMI bit set in the exit qualification to KVM instead of EXIT_REASON_EXCEPTION_NMI with MC exception. Handle EXIT_REASON_OTHER_SMI with MSMI bit set in the exit qualification as MCE(Machine Check Exception) happened during TD guest running. Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/tdx.c | 40 ++++++++++++++++++++++++++++++++++--- arch/x86/kvm/vmx/tdx_arch.h | 2 ++ 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/vmx/tdx.c b/arch/x86/kvm/vmx/tdx.c index 45b521e05ceb..e56eeb8d0ec7 100644 --- a/arch/x86/kvm/vmx/tdx.c +++ b/arch/x86/kvm/vmx/tdx.c @@ -796,6 +796,30 @@ void tdx_handle_exit_irqoff(struct kvm_vcpu *vcpu) tdexit_intr_info(vcpu)); else if (exit_reason =3D=3D EXIT_REASON_EXCEPTION_NMI) vmx_handle_exception_irqoff(vcpu, tdexit_intr_info(vcpu)); + else if (unlikely(tdx->exit_reason.non_recoverable || + tdx->exit_reason.error)) { + /* + * The only reason it gets EXIT_REASON_OTHER_SMI is there is an + * #MSMI(Machine Check System Management Interrupt) with + * exit_qualification bit 0 set in TD guest. + * The #MSMI is delivered right after SEAMCALL returns, + * and an #MC is delivered to host kernel after SMI handler + * returns. + * + * The #MC right after SEAMCALL is fixed up and skipped in #MC + * handler because it's an #MC happens in TD guest we cannot + * handle it with host's context. + * + * Call KVM's machine check handler explicitly here. + */ + if (tdx->exit_reason.basic =3D=3D EXIT_REASON_OTHER_SMI) { + unsigned long exit_qual; + + exit_qual =3D tdexit_exit_qual(vcpu); + if (exit_qual & TD_EXIT_OTHER_SMI_IS_MSMI) + kvm_machine_check(); + } + } } =20 static int tdx_handle_exception(struct kvm_vcpu *vcpu) @@ -1229,6 +1253,11 @@ int tdx_handle_exit(struct kvm_vcpu *vcpu, fastpath_= t fastpath) exit_reason.full, exit_reason.basic, to_kvm_tdx(vcpu->kvm)->hkid, set_hkid_to_hpa(0, to_kvm_tdx(vcpu->kvm)->hkid)); + + /* + * tdx_handle_exit_irqoff() handled EXIT_REASON_OTHER_SMI. It + * must be handled before enabling preemption because it's #MC. + */ goto unhandled_exit; } =20 @@ -1267,9 +1296,14 @@ int tdx_handle_exit(struct kvm_vcpu *vcpu, fastpath_= t fastpath) return tdx_handle_ept_misconfig(vcpu); case EXIT_REASON_OTHER_SMI: /* - * If reach here, it's not a Machine Check System Management - * Interrupt(MSMI). #SMI is delivered and handled right after - * SEAMRET, nothing needs to be done in KVM. + * Unlike VMX, all the SMI in SEAM non-root mode (i.e. when + * TD guest vcpu is running) will cause TD exit to TDX module, + * then SEAMRET to KVM. Once it exits to KVM, SMI is delivered + * and handled right away. + * + * - If it's an Machine Check System Management Interrupt + * (MSMI), it's handled above due to non_recoverable bit set. + * - If it's not an MSMI, don't need to do anything here. */ return 1; default: diff --git a/arch/x86/kvm/vmx/tdx_arch.h b/arch/x86/kvm/vmx/tdx_arch.h index 942a0e561a7b..8860c7571b1f 100644 --- a/arch/x86/kvm/vmx/tdx_arch.h +++ b/arch/x86/kvm/vmx/tdx_arch.h @@ -46,6 +46,8 @@ #define TDG_VP_VMCALL_REPORT_FATAL_ERROR 0x10003 #define TDG_VP_VMCALL_SETUP_EVENT_NOTIFY_INTERRUPT 0x10004 =20 +#define TD_EXIT_OTHER_SMI_IS_MSMI BIT(1) + /* TDX control structure (TDR/TDCS/TDVPS) field access codes */ #define TDX_NON_ARCH BIT_ULL(63) #define TDX_CLASS_SHIFT 56 --=20 2.25.1