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Wed, 9 Oct 2024 09:38:53 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 11/11] iommu/arm-smmu-v3: Add IOMMU_VIOMMU_TYPE_ARM_SMMUV3 support Date: Wed, 9 Oct 2024 09:38:11 -0700 Message-ID: <562f2bfae1661e6ff6abdb280faa0dd49df9fbdc.1728491453.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099E2:EE_|IA0PR12MB7601:EE_ X-MS-Office365-Filtering-Correlation-Id: a20c2570-0e14-4ab2-32a1-08dce880e1ca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?/ANdbQzA9G8jnzbou7rq1e+I+Cai09rWasWnUsQOcR6bb9b38p7audkKdF9H?= =?us-ascii?Q?9zQ9pY7TuNu5KRTmSvhTvGnvk+LJMO7WVh7oGjoU7VrixAbWejaVWCWSiIok?= =?us-ascii?Q?ttOoUzlgvanBVba2B2hZRpNkQhLDe1O10zUNvj9aagpuEN+zHLmfVGVfMeVP?= =?us-ascii?Q?Vqt+yH6Rd74QHMgbajIQvaXvSsx7Iuzh6q6sR6tNnj8FupluGNVyQ3vcZqTn?= =?us-ascii?Q?TKkv+Ms2gwNRPTsPdY+dWkzPLS/Uf181hQ0Ug9h7OySY3A4iqOE5pQtTvNnS?= =?us-ascii?Q?IyoySZwkN7/Cp9wOR2gpgxiFtXCQyqLUjpr35RqI4QGG4W5JJJOumkLS5pnZ?= =?us-ascii?Q?c5lYfeqBkHw1GLwXUSWwCLV6WXEKYmMIvLL3dhwyuADDIAo2A9kgHMdM5tS2?= =?us-ascii?Q?mpoOAb12f/yZfAbujsRctGtUy+7Dv+MUmcwFrlyKaUyBLI9KfPC7/3a1zzp3?= =?us-ascii?Q?FNdEfg+jqlPUPLDq/mJAPiqnBzmmKvzTmn0/cUaZ5rZlZlc4Z0FAHevI95Gq?= =?us-ascii?Q?3CYX0nQAM2PJyKJiYfJXZ4ls1cisBwePeNcuDtwdLVkKz6jOs7fKNw5C7q86?= =?us-ascii?Q?eEK2xbLZbXuFprFDTRrOpL0DoqVJcsJkN/XFpRzEeKNkYNjYYHi60U70DlR5?= =?us-ascii?Q?64Jy5EJOLI3cVie3QDoAiTUQeq6fhqpZgYShxZ/teCGPxoKWcA3xA5zgON3C?= =?us-ascii?Q?zESEGdTrJx+c9Ul8VkNAaIjppsnup0gea0pSzlwUwU/Vz3Re0O6nKjQYJXRL?= =?us-ascii?Q?p3TMgPTCr/mleKF0G4Wg3GUWisQbfgsEHRogMgvAbYGq9TCkjYXfx3+UTf3R?= =?us-ascii?Q?YTnGyxxy8cSWOlZjulVO/IQ0y1ZMfHmiHLllegnolIP5ONQvbcX/GWtDFWj5?= =?us-ascii?Q?0QaZIkOhtzlRbBUOmfeBhQmu9K7t/XNI1I6SMzHxd23kV4JYs3/csi62INhd?= =?us-ascii?Q?ojGPfuGiFkcwSLuPmVoCQCxYfPWCIPN746BDKZONGstXwUSCCW8+wKQEBu00?= =?us-ascii?Q?0RKzWzm4yZeHQaK4HBa/NPnbq7UdTE/XjxQLDF93AGMvyjw1xvOhJ6xruK52?= =?us-ascii?Q?yQUcbmLnv6g0Er0Ryl2iT9erOfbqeq0okyUDwfgHv5xJdgnlC+vUGZY0SKoG?= =?us-ascii?Q?W5ZXYq0VtDwC0vuOHyK1kNJK5n37SBHeTsIx/UEuet2p/P7nH5M5FNSmhwZW?= =?us-ascii?Q?FLpSxcy7d4aztvWYPDh0/AF45J2MSnM2qlIfXGqwG/JvNWDrjWm7AhVgpcVy?= =?us-ascii?Q?zSmCaRkKzF4hPFb3cnQS+OjHKi1a3MFkG00SfxH1brYnhyR+YOJH5c5vZv6L?= =?us-ascii?Q?+zAn8W6guLMImqDzdVOqRvrpAxaUkw0x4c3udy+F57PzgzdHc0Img68RpAoZ?= =?us-ascii?Q?syQI3hs5BqiHcVOiwyG+sslTrKB5?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Oct 2024 16:39:02.0100 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a20c2570-0e14-4ab2-32a1-08dce880e1ca X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099E2.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7601 Content-Type: text/plain; charset="utf-8" Add a new driver-type for ARM SMMUv3 to enum iommu_viommu_type. Implement the viommu_alloc op with an arm_vsmmu_alloc function. As an initial step, copy the VMID from s2_parent. A later cleanup series is required to move the VMID allocation out of the stage-2 domain allocation routine to this. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 18 ++++++++++++++ include/uapi/linux/iommufd.h | 2 ++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 24 +++++++++++++++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1 + 4 files changed, 45 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index e394943c0b4b..844d1dfdea55 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include @@ -1005,12 +1006,22 @@ tegra241_cmdqv_probe(struct arm_smmu_device *smmu) } #endif /* CONFIG_TEGRA241_CMDQV */ =20 +struct arm_vsmmu { + struct iommufd_viommu core; + struct arm_smmu_device *smmu; + struct arm_smmu_domain *s2_parent; + u16 vmid; +}; + #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type); struct iommu_domain * arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, struct iommu_domain *parent, const struct iommu_user_data *user_data); +struct iommufd_viommu * +arm_vsmmu_alloc(struct iommu_device *iommu_dev, struct iommu_domain *paren= t, + struct iommufd_ctx *ictx, unsigned int viommu_type); #else #define arm_smmu_hw_info NULL static inline struct iommu_domain * @@ -1020,6 +1031,13 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u3= 2 flags, { return ERR_PTR(-EOPNOTSUPP); } + +static inline struct iommufd_viommu * +arm_vsmmu_alloc(struct iommu_device *iommu_dev, struct iommu_domain *paren= t, + struct iommufd_ctx *ictx, unsigned int viommu_type) +{ + return ERR_PTR(-EOPNOTSUPP); +} #endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */ =20 #endif /* _ARM_SMMU_V3_H */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index ff8aece8212f..6ee841a8c79b 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -857,9 +857,11 @@ struct iommu_fault_alloc { /** * enum iommu_viommu_type - Virtual IOMMU Type * @IOMMU_VIOMMU_TYPE_DEFAULT: Core-managed virtual IOMMU type + * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT =3D 0, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3 =3D 1, }; =20 /** diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 51260f63be94..5e235fca8f13 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -212,3 +212,27 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 = flags, =20 return &nested_domain->domain; } + +struct iommufd_viommu * +arm_vsmmu_alloc(struct iommu_device *iommu_dev, struct iommu_domain *paren= t, + struct iommufd_ctx *ictx, unsigned int viommu_type) +{ + struct arm_smmu_device *smmu =3D + container_of(iommu_dev, struct arm_smmu_device, iommu); + struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent); + struct arm_vsmmu *vsmmu; + + if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return ERR_PTR(-EOPNOTSUPP); + + vsmmu =3D iommufd_viommu_alloc(ictx, arm_vsmmu, core, NULL); + if (IS_ERR(vsmmu)) + return ERR_CAST(vsmmu); + + vsmmu->smmu =3D smmu; + vsmmu->s2_parent =3D s2_parent; + /* FIXME Move VMID allocation from the S2 domain allocation to here */ + vsmmu->vmid =3D s2_parent->s2_cfg.vmid; + + return &vsmmu->core; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 4b836a5e9fde..6a23e6dcd5cf 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3541,6 +3541,7 @@ static struct iommu_ops arm_smmu_ops =3D { .dev_disable_feat =3D arm_smmu_dev_disable_feature, .page_response =3D arm_smmu_page_response, .def_domain_type =3D arm_smmu_def_domain_type, + .viommu_alloc =3D arm_vsmmu_alloc, .pgsize_bitmap =3D -1UL, /* Restricted during device attach */ .owner =3D THIS_MODULE, .default_domain_ops =3D &(const struct iommu_domain_ops) { --=20 2.43.0