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Thu, 18 Dec 2025 12:27:17 -0800 From: Nicolin Chen To: , , CC: , , , , , , , Subject: [PATCH v1 4/9] iommu/arm-smmu-v3: Use alloc_id/free_id ops in arm_smmu_invs_merge/unref Date: Thu, 18 Dec 2025 12:26:50 -0800 Message-ID: <54c98cd7092a406d84df0abc9a6cb013aadb619a.1766088962.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD7:EE_|SN7PR12MB6886:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ba6ff14-5769-4cde-3500-08de3e73e489 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?eMhFRs+1wVxU67L+VHrH9D/DgqnPeyiDNBUO9Jp1W/KlAjMzCjjeGnl7sFHB?= =?us-ascii?Q?pBOZ3i/76aAOxd+pwFnKbvEAGe24UiTddPFcvlwjnFrN4/W0Z+rIJ3b+gJ0T?= =?us-ascii?Q?K+X14IYGz2k5bkvcusIjPTUIPNZdJWlODKQuAyLooA+c+bgvkZf5YOBbTXaK?= =?us-ascii?Q?pE5pb+SWe2o9cn8DX0uiXJ6TQcYkD4mj9u0YazUM1Zr61lG38J5SzF7IDDs5?= =?us-ascii?Q?x80xWmjzs2o4mLvEpJUlTMs9LhY+H0KZfQMRoZPhs9vKneXsCUnmzs10Qz8V?= =?us-ascii?Q?wBgV8InaM4JlZKpmCdv7N+JgLwiCsEROJ4ypzTM9zbL7SaoyC9OATwsUpA+d?= =?us-ascii?Q?IEnPwbDljTFXvu+adpJtTH57AL7oir8J+dcHc/MZvBJD4T0YNlWrpzmClhCI?= =?us-ascii?Q?m4/zmYBWfK6tE70bnU6vCH83HeSS672yqI/HREidZhkgzpszmi1uyijo2i+w?= =?us-ascii?Q?JABc9oIAPihRry+HUYxx3hf31hvBAm1COhYt/v+QKo3GMUzoY1zX/BFS8tYR?= =?us-ascii?Q?bDPM/itM6bTLc9PmfYJ0YVi30L+8gJ/ccW2b3Hn99mTfs/i7EDqYh9ZcO3Jx?= =?us-ascii?Q?OpEh6sYysIXhlVI1+y6a+Mdxde/hzIl6KpDizwgTyN+3QaOUf1Gsoe6CGOaC?= =?us-ascii?Q?G9jfToK9QBeI4Z8Jnq60xHyq6d8Q55foT4rzc5kBrEUWe3iJOtwXh0g4PVBr?= =?us-ascii?Q?1ZERD/awISL2utgXonfsimtG/+ZYwZu+J1RcQfi/JFQJsd+9qRjXq+UNAWCc?= =?us-ascii?Q?zIjE4cXETYLobiOxujzVEQBGRa+BMDD0C5Km0+KIcx9WLwbMLye3EBNb59Wy?= =?us-ascii?Q?AJLYa7DrLTQVgy22/ZwpxWGExvhKNFyH54i240mvNAHTkAb7lFLUplSwwUjC?= =?us-ascii?Q?cjPC4Qkze7fACFMKEV46OiVcCLL54t5pj2Ws/nuImMQRfN1zAziDqKSMs7IS?= =?us-ascii?Q?S7EWRMSZBHlee7djoJk9/cVWNVXvkABkQpCWKbOKmNRGyUgKSS5zYbWrxAh1?= =?us-ascii?Q?czzpgA9d2GUOeuGeYbTBcV43nIti4KVqTGrlwYVoyXlzdGfsPB4fYamGzkAm?= =?us-ascii?Q?QSw5awmfQQrI5Q9/MIAnruVGdsDH9E95MpJ6k60r+zRRndgr3iwNp01v2ZHQ?= =?us-ascii?Q?qImC++a8A9c9C+PaOSUpOPNDBlnHYMgoREEMc/gnMagQixOePkrZuPzOZa1d?= =?us-ascii?Q?vgo3JBDWEMZgWyiiazpzwlMfJI51wSm2xrOxrzxmlAMD038i1TnYSBO2NU0r?= =?us-ascii?Q?FxqNgLEjKc3b2PAivDuqCvz/t5dGMSr5E/SYzEuraehiVtOKOFm0kAciJHS5?= =?us-ascii?Q?f/0q9k3FR8/UjYkKhh2RY40Bzw9zN0zeJC/Ibjp2IjtXSJKot+ao4C7WG+4f?= =?us-ascii?Q?xq3lIP/3RrLIPjZbi57cd4Nx1uaUNnS9QOjVLl+gcu2sqTq9aZK2GBzj9O0I?= =?us-ascii?Q?XDcY4icM2YP/QpN0HH+5Q6IzgsaYH4E4dkG/9NRf8WwrQGC/5Wbw2NMUdrLb?= =?us-ascii?Q?U3rPzm2ogauPMGFlWmVjQjP2PKglsaDnx9izY1AA7R2u0ry7wypMpRaZU+9u?= =?us-ascii?Q?2DRxtYnL0RygSmvtSSQ=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Dec 2025 20:27:40.8210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ba6ff14-5769-4cde-3500-08de3e73e489 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB6886 Content-Type: text/plain; charset="utf-8" If a domain->invs has an iotlb tag (ASID/VMID) for an SMMU, all the devices behind the SMMU can reuse the same iotlb tag. This exactly matches with the existing case where attaching multiple devices to the same SMMU domain has a shared iotlb tag stored in the domain (cd->asid or s2_cfg->vmid). If a domain->invs doesn't have an iotlb tag for another SMMU, there can be two cases: 1) This is a new domain so not yet attached to any devices 2) This is a shareable domain that is attached to a device behind one SMMU but not yet to the other SMMU. In either case, a new iotlb tag is required. Call the ->alloc_id op in the arm_smmu_invs_merge(). The domain->invs arrary will keep it. The allocated new iotlb tag will be returned to the caller via to_merge arrary. Relax the arm_smmu_inv_cmp(), to allow sharing an iotlb tag across devices behind the same SMMU instance. Similarly, call the ->free_id op in the arm_smmu_invs_unref() when there's no device using it any more. Lastly, add a free helper for the revert path of arm_smmu_attach_prepare() to use. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 70 +++++++++++++++++++-- 2 files changed, 69 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index e21e95936b05..230ab902a9b6 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -680,6 +680,9 @@ static inline bool arm_smmu_inv_is_ats(const struct arm= _smmu_inv *inv) return inv->type =3D=3D INV_TYPE_ATS || inv->type =3D=3D INV_TYPE_ATS_FUL= L; } =20 +/* S1_ASID/S2_VMID(S1_CLEAR) types */ +#define arm_smmu_inv_is_iotlb_tag(inv) !arm_smmu_inv_is_ats(inv) + /** * struct arm_smmu_invs - Per-domain invalidation array * @max_invs: maximum capacity of the flexible array diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 1bf7b7233109..ec370e54b1bc 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1051,6 +1051,9 @@ static int arm_smmu_inv_cmp(const struct arm_smmu_inv= *inv_l, return cmp_int((uintptr_t)inv_l->smmu, (uintptr_t)inv_r->smmu); if (inv_l->type !=3D inv_r->type) return cmp_int(inv_l->type, inv_r->type); + /* Each SMMU shares a single iotlb tag on a domain, so it is a match */ + if (arm_smmu_inv_is_iotlb_tag(inv_l)) + return 0; return cmp_int(inv_l->id, inv_r->id); } =20 @@ -1127,9 +1130,52 @@ struct arm_smmu_invs *arm_smmu_invs_merge(struct arm= _smmu_invs *invs, size_t i, j; int cmp; =20 - arm_smmu_invs_for_each_cmp(invs, i, to_merge, j, cmp) + arm_smmu_invs_for_each_cmp(invs, i, to_merge, j, cmp) { + struct arm_smmu_inv *cur =3D &to_merge->inv[j]; + num_invs++; =20 + if (!arm_smmu_inv_is_iotlb_tag(cur)) + continue; + + /* A matching iotlb tag owned by the same SMMU can be shared */ + if (cmp =3D=3D 0) { + *cur =3D invs->inv[i]; + continue; + } + + /* Iterate the base invs array to find if next is a match */ + if (cmp < 0 && i < invs->num_invs) + continue; + + /* + * Currently the @to_merge array always carries an id (> 0) that + * is also installed in the CD/STE. So, we cannot allocate a new + * ID at this moment, because that would misalign with what's in + * the CD/STE. To not break the existing flow, bypass the new ID + * allocating code. We will lift this bypass line once rework is + * done. + */ + if (cur->id) + continue; + + /* No found. Allocate a new one */ + if (j =3D=3D 0) { + /* KUNIT test doesn't pass in an alloc_id function */ + if (to_merge->alloc_id) { + int ret; + + ret =3D to_merge->alloc_id(cur, + invs->smmu_domain); + if (ret) + return ERR_PTR(ret); + } + } else { + /* Copy the allocated iotlb tag from the previous inv */ + cur->id =3D cur[-1].id; + } + } + new_invs =3D arm_smmu_invs_alloc(num_invs); if (!new_invs) return ERR_PTR(-ENOMEM); @@ -1207,9 +1253,9 @@ void arm_smmu_invs_unref(struct arm_smmu_invs *invs, continue; } =20 - /* KUNIT test doesn't pass in a free_fn */ - if (free_fn) - free_fn(&invs->inv[i]); + /* KUNIT test doesn't pass in a free_id function */ + if (to_unref->free_id) + to_unref->free_id(&invs->inv[i], true); invs->num_trashes++; } else { /* item in to_unref is not in invs or already a trash */ @@ -3167,6 +3213,21 @@ static void arm_smmu_inv_free_vmid(struct arm_smmu_i= nv *inv, bool flush) ida_free(&inv->smmu->vmid_map, inv->id); } =20 +static void arm_smmu_inv_free_iotlb_tag(struct arm_smmu_inv *inv) +{ + switch (inv->type) { + case INV_TYPE_S1_ASID: + arm_smmu_inv_free_asid(inv, false); + return; + case INV_TYPE_S2_VMID: + arm_smmu_inv_free_vmid(inv, false); + return; + default: + WARN_ON(true); + return; + } +} + static int arm_smmu_inv_alloc_asid(struct arm_smmu_inv *inv, void *data) { struct arm_smmu_domain *smmu_domain =3D data; @@ -3662,6 +3723,7 @@ int arm_smmu_attach_prepare(struct arm_smmu_attach_st= ate *state, err_free_vmaster: kfree(state->vmaster); err_unprepare_invs: + arm_smmu_inv_free_iotlb_tag(&state->new_domain_invst.iotlb_tag); kfree(state->new_domain_invst.new_invs); return ret; } --=20 2.43.0