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Wed, 14 May 2025 07:09:55 -0700 (PDT) From: Han Gao To: devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Han Gao , Thomas Bonnefille , Guo Ren , Chao Wei , sophgo@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree Date: Wed, 14 May 2025 22:09:02 +0800 Message-ID: <53a9a794641af697be9170e6d0af464a39d862ae.1747231254.git.rabenda.cn@gmail.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Sophgo SG2042_EVB_V2.0 [1] is a prototype development board based on SG2042 Currently supports serial port, sdcard/emmc, pwm, fan speed control. Link: https://github.com/sophgo/sophgo-hardware/tree/master/SG2042/SG2042-x= 4-EVB [1] Signed-off-by: Han Gao --- arch/riscv/boot/dts/sophgo/Makefile | 1 + arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 235 +++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/soph= go/Makefile index 2470e30ae901..31fa46ef3bf6 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -4,3 +4,4 @@ dtb-$(CONFIG_ARCH_SOPHGO) +=3D cv1812h-huashan-pi.dtb dtb-$(CONFIG_ARCH_SOPHGO) +=3D sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_ARCH_SOPHGO) +=3D sg2042-milkv-pioneer.dtb dtb-$(CONFIG_ARCH_SOPHGO) +=3D sg2042-evb-v1.dtb +dtb-$(CONFIG_ARCH_SOPHGO) +=3D sg2042-evb-v2.dtb diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot= /dts/sophgo/sg2042-evb-v2.dts new file mode 100644 index 000000000000..8eba1a4ab1ee --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Sophgo Technology Inc. All rights reserved. + */ + +#include "sg2042.dtsi" + +#include +#include + +/ { + model =3D "Sophgo SG2042 EVB V2.0"; + compatible =3D "sophgo,sg2042-evb-v2", "sophgo,sg2042"; + + chosen { + stdout-path =3D "serial0"; + }; +}; + +&cgi_main { + clock-frequency =3D <25000000>; +}; + +&cgi_dpll0 { + clock-frequency =3D <25000000>; +}; + +&cgi_dpll1 { + clock-frequency =3D <25000000>; +}; + +&emmc { + pinctrl-0 =3D <&emmc_cfg>; + pinctrl-names =3D "default"; + bus-width =3D <4>; + no-sdio; + no-sd; + non-removable; + wp-inverted; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-0 =3D <&i2c1_cfg>; + pinctrl-names =3D "default"; + status =3D "okay"; + + mcu: syscon@17 { + compatible =3D "sophgo,sg2042-hwmon-mcu"; + reg =3D <0x17>; + #thermal-sensor-cells =3D <1>; + }; +}; + +&gmac0 { + phy-handle =3D <&phy0>; + phy-mode =3D "rgmii-id"; + status =3D "okay"; + + mdio { + phy0: phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + reset-gpios =3D <&port0a 27 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <100000>; + reset-deassert-us =3D <100000>; + }; + }; +}; + +&pinctrl { + emmc_cfg: sdhci-emmc-cfg { + sdhci-emmc-wp-pins { + pinmux =3D ; + bias-disable; + drive-strength-microamp =3D <26800>; + input-schmitt-disable; + }; + + sdhci-emmc-cd-pins { + pinmux =3D ; + bias-pull-up; + drive-strength-microamp =3D <26800>; + input-schmitt-enable; + }; + + sdhci-emmc-rst-pwr-pins { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <26800>; + input-schmitt-disable; + }; + }; + + i2c1_cfg: i2c1-cfg { + i2c1-pins { + pinmux =3D , + ; + bias-pull-up; + drive-strength-microamp =3D <26800>; + input-schmitt-enable; + }; + }; + + sd_cfg: sdhci-sd-cfg { + sdhci-sd-cd-wp-pins { + pinmux =3D , + ; + bias-pull-up; + drive-strength-microamp =3D <26800>; + input-schmitt-enable; + }; + + sdhci-sd-rst-pwr-pins { + pinmux =3D , + ; + bias-disable; + drive-strength-microamp =3D <26800>; + input-schmitt-disable; + }; + }; + + uart0_cfg: uart0-cfg { + uart0-rx-pins { + pinmux =3D , + ; + bias-pull-up; + drive-strength-microamp =3D <26800>; + input-schmitt-enable; + }; + }; +}; + +&sd { + pinctrl-0 =3D <&sd_cfg>; + pinctrl-names =3D "default"; + bus-width =3D <4>; + no-sdio; + no-mmc; + wp-inverted; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_cfg>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +/ { + pwmfan: pwm-fan { + compatible =3D "pwm-fan"; + cooling-levels =3D <103 128 179 230 255>; + pwms =3D <&pwm 0 40000 0>; + #cooling-cells =3D <2>; + }; + + thermal-zones { + soc-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + thermal-sensors =3D <&mcu 0>; + + trips { + soc_active1: soc-active1 { + temperature =3D <30000>; + hysteresis =3D <8000>; + type =3D "active"; + }; + + soc_active2: soc-active2 { + temperature =3D <58000>; + hysteresis =3D <12000>; + type =3D "active"; + }; + + soc_active3: soc-active3 { + temperature =3D <70000>; + hysteresis =3D <10000>; + type =3D "active"; + }; + + soc_hot: soc-hot { + temperature =3D <80000>; + hysteresis =3D <5000>; + type =3D "hot"; + }; + }; + + cooling-maps { + map0 { + trip =3D <&soc_active1>; + cooling-device =3D <&pwmfan 0 1>; + }; + + map1 { + trip =3D <&soc_active2>; + cooling-device =3D <&pwmfan 1 2>; + }; + + map2 { + trip =3D <&soc_active3>; + cooling-device =3D <&pwmfan 2 3>; + }; + + map3 { + trip =3D <&soc_hot>; + cooling-device =3D <&pwmfan 3 4>; + }; + }; + }; + + board-thermal { + polling-delay-passive =3D <1000>; + polling-delay =3D <1000>; + thermal-sensors =3D <&mcu 1>; + + trips { + board_active: board-active { + temperature =3D <75000>; + hysteresis =3D <8000>; + type =3D "active"; + }; + }; + + cooling-maps { + map4 { + trip =3D <&board_active>; + cooling-device =3D <&pwmfan 3 4>; + }; + }; + }; + }; +}; --=20 2.47.2