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[81.204.249.205]) by smtp.gmail.com with ESMTPSA id p14-20020a170906140e00b009786ae9ed50sm9599908ejc.194.2023.06.15.10.34.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 15 Jun 2023 10:34:14 -0700 (PDT) Message-ID: <539cfba7-dd6f-015e-b990-a2335cb3aac9@gmail.com> Date: Thu, 15 Jun 2023 19:34:13 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 From: Johan Jonker Subject: [PATCH v3 2/3] mtd: rawnand: rockchip-nand-controller: copy hwecc PA data to oob_poi buffer To: miquel.raynal@bootlin.com Cc: richard@nod.at, vigneshr@ti.com, heiko@sntech.de, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, yifeng.zhao@rock-chips.com References: <0047fc52-bc45-a768-8bdd-c0f12cddc17e@gmail.com> Content-Language: en-US In-Reply-To: <0047fc52-bc45-a768-8bdd-c0f12cddc17e@gmail.com> Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Rockchip boot blocks are written per 4 x 512 byte sectors per page. Each page must have a page address (PA) pointer in OOB to the next page. Pages are written in a pattern depending on the NAND chip ID. This logic used to build a page pattern table is not fully disclosed and is not easy to fit in the MTD framework. The formula in rk_nfc_write_page_hwecc() function is not correct. Make hwecc and raw behavior identical. Generate boot block page address and pattern for hwecc in user space and copy PA data to/from the already reserved last 4 bytes before EEC in the chip->oob_poi data layout. This patch breaks all existing jffs2 users that have free OOB overlap with the reserved space for PA data. Signed-off-by: Johan Jonker --- Changed V3: Change prefixes Reword --- .../mtd/nand/raw/rockchip-nand-controller.c | 34 ++++++++++++------- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/raw/rockchip-nand-controller.c b/drivers/mtd/= nand/raw/rockchip-nand-controller.c index 37fc07ba5..5a0468034 100644 --- a/drivers/mtd/nand/raw/rockchip-nand-controller.c +++ b/drivers/mtd/nand/raw/rockchip-nand-controller.c @@ -598,7 +598,7 @@ static int rk_nfc_write_page_hwecc(struct nand_chip *ch= ip, const u8 *buf, int pages_per_blk =3D mtd->erasesize / mtd->writesize; int ret =3D 0, i, boot_rom_mode =3D 0; dma_addr_t dma_data, dma_oob; - u32 reg; + u32 tmp; u8 *oob; nand_prog_page_begin_op(chip, page, 0, NULL, 0); @@ -625,6 +625,13 @@ static int rk_nfc_write_page_hwecc(struct nand_chip *c= hip, const u8 *buf, * * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... * + * The code here just swaps the first 4 bytes with the last + * 4 bytes without losing any data. + * + * The chip->oob_poi data layout: + * + * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 + * * Configure the ECC algorithm supported by the boot ROM. */ if ((page < (pages_per_blk * rknand->boot_blks)) && @@ -635,21 +642,17 @@ static int rk_nfc_write_page_hwecc(struct nand_chip *= chip, const u8 *buf, } for (i =3D 0; i < ecc->steps; i++) { - if (!i) { - reg =3D 0xFFFFFFFF; - } else { + if (!i) + oob =3D chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; + else oob =3D chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; - reg =3D oob[0] | oob[1] << 8 | oob[2] << 16 | - oob[3] << 24; - } - if (!i && boot_rom_mode) - reg =3D (page & (pages_per_blk - 1)) * 4; + tmp =3D oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24; if (nfc->cfg->type =3D=3D NFC_V9) - nfc->oob_buf[i] =3D reg; + nfc->oob_buf[i] =3D tmp; else - nfc->oob_buf[i * (oob_step / 4)] =3D reg; + nfc->oob_buf[i * (oob_step / 4)] =3D tmp; } dma_data =3D dma_map_single(nfc->dev, (void *)nfc->page_buf, @@ -812,12 +815,17 @@ static int rk_nfc_read_page_hwecc(struct nand_chip *c= hip, u8 *buf, int oob_on, goto timeout_err; } - for (i =3D 1; i < ecc->steps; i++) { - oob =3D chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + for (i =3D 0; i < ecc->steps; i++) { + if (!i) + oob =3D chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; + else + oob =3D chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; + if (nfc->cfg->type =3D=3D NFC_V9) tmp =3D nfc->oob_buf[i]; else tmp =3D nfc->oob_buf[i * (oob_step / 4)]; + *oob++ =3D (u8)tmp; *oob++ =3D (u8)(tmp >> 8); *oob++ =3D (u8)(tmp >> 16); -- 2.30.2