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Mon, 26 Jan 2026 19:09:37 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v10 5/8] iommu/arm-smmu-v3: Pre-allocate a per-master invalidation array Date: Mon, 26 Jan 2026 19:09:16 -0800 Message-ID: <5270d84e09276a8368b413a2d9ef69deea03474b.1769476588.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD83:EE_|DM4PR12MB5796:EE_ X-MS-Office365-Filtering-Correlation-Id: a77b1f4b-bd76-4926-55b4-08de5d51878d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?mjDPT1iLFzcdP+Mgt9N1CWV1IMViVGoQ8BuLVouEFcpia1fjxjJBb9Z29BI+?= =?us-ascii?Q?a4QJk4OHOj8RwkGkKCvut3ecRVwPHEIhmB78VQyh+2csqwLVkBvsgUisC0MF?= =?us-ascii?Q?FpwkUVcI4PRFpnQANnLA+cMudwRpmG/V3K49KFzriLwOWlJx+oeFqPVZiIxv?= =?us-ascii?Q?Sy7HbMZcZJ+0fc8UofyX3ChPRZJ9e98L0iT0eot9Zr7gss+luHMoaI6olGay?= =?us-ascii?Q?Tl8Oi/SWtpblqPZRD8snRLafE2cef0VVQ+CrgDkwzArHN3+AiuBSXvXwB0DB?= =?us-ascii?Q?aCwWvkPO14TM1uBtz+E1m041Cj5+8klD2AnA2etXha7dZXpPCfCt5dTgf+yF?= =?us-ascii?Q?pVxYjiUckZfHZTa1LI5ZIQAwi8smCJ5aFLKz83PbMLqcboz9/0WFJuMhpLNm?= =?us-ascii?Q?llxvnjxPVB0W6g7KipG/lzLWT90ltnK13yqzov+wdgj4R/YlVjFARHRrW8kF?= =?us-ascii?Q?2YrnlT8mXU7IQp4eaIg+ZroUCy89IPEKsf/w92H3qD+rzh3HhuVyZTtOiurl?= =?us-ascii?Q?YYknM+4+x9KLp4G6re71zuydzyIGwadTKBY15DqHBxXqM4RosiLcIAdA/5vw?= =?us-ascii?Q?2+jsiBnOoxEGuo9+Wz12HD094TIzo4RPQaYLs9PMBytiZQ93zs9b33PcR7CR?= =?us-ascii?Q?XkMW+gnb+dtpCRBkmF4Tr4FXrmswmgwssa8DOHeuPwuVDCokFT4bHyKes2Ns?= =?us-ascii?Q?5MuqZeAz30/8RNAcsv9IS5jVJ9dCga57WybRHiVMIjSv+Nh4dwJH9CTx+Nnx?= =?us-ascii?Q?3OYoWtOT0GGLt7HtoNuF8to7qr+spfTS6T/YS7k5jo5pjW6NwSPpI7V7FLyL?= =?us-ascii?Q?FcTAx2PUDR8xIkzRGVPvLaLiDRMm+ey/8XLcSjH7tIKdoW1kdv+FNztHrxZO?= =?us-ascii?Q?VeUwwIrP8SgrkwgAucsG6V3gDKGb55AvSgEnxutaujoDPmEdaQQ6nme5wqzl?= =?us-ascii?Q?ef+sgERoeIG7ssr51cM6ulOLeQhQ0uckZf+PYW3Ody4MttW/2xJUsIYTr6Kx?= =?us-ascii?Q?eKy64lQ3wGI6huwHLaMQ5ioZLI8uDpBma69OPZq8CI52BxxwZiQrTxRJJbIV?= =?us-ascii?Q?BikF9yGOQZ+OnACtAtyjaDLig/KStTnsBGJ2+rqnhjxx8aEvGR7CuNZa9WHE?= =?us-ascii?Q?NcCHq8f7G76xZXOvOfG3SoHW5dbvYyZA4xZQL6seJtuz0d5tPRA8BpA5doJu?= =?us-ascii?Q?QOW8j73ITZCo8W7kBcB7fQ7ezaYIRk0lF0qxkh7RJ1JXdfza8y5nk2ggybhG?= =?us-ascii?Q?ZNMUo/tKUn5FTZFNkZr9PnG4hhSe3Ol3/vDi9brfUX4rK50uNhwRTYV9Agoy?= =?us-ascii?Q?4RizCdYftJ8swOdc+DhDzh0MvnqrQOakBW0yOYXwnew5cdg2O/ibi+DK6WxB?= =?us-ascii?Q?9VLJIjtn0jiOktIVd/mtoZY1PaSplj/IdN8nFPa9Ru+uY/VunTMJ5/e3wST7?= =?us-ascii?Q?FJpcFlYFG97iW4+EQCOm//6EWd+Kiizksn5kd5FsMUNhULF2cCmsw1WPod11?= =?us-ascii?Q?e+tQiuMHmMJhI1iiad3mXSkOsXzBh7dy36TpN7a4gQi6rwIQa99yM5bJ2xZ5?= =?us-ascii?Q?hyMfjmTOsHVXDrtBGChLwVB/2sN6cOOqycs2/syAYZPmlFQMSP9jnAA1kZ66?= =?us-ascii?Q?lWiYHFj+Z2PlxC9VjR+7Mf0PSTQN94dNrh7SQD/NTUO0WKA5mIoJo1nttL0x?= =?us-ascii?Q?tWwtAw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2026 03:09:47.9629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a77b1f4b-bd76-4926-55b4-08de5d51878d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD83.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5796 Content-Type: text/plain; charset="utf-8" When a master is attached from an old domain to a new domain, it needs to build an invalidation array to delete and add the array entries from/onto the invalidation arrays of those two domains, passed via the to_merge and to_unref arguments into arm_smmu_invs_merge/unref() respectively. Since the master->num_streams might differ across masters, a memory would have to be allocated when building an to_merge/to_unref array which might fail with -ENOMEM. On the other hand, an attachment to arm_smmu_blocked_domain must not fail so it's the best to avoid any memory allocation in that path. Pre-allocate a fixed size invalidation array for every master. This array will be used as a scratch to fill dynamically when building a to_merge or to_unref invs array. Sort fwspec->ids in an ascending order to fit to the arm_smmu_invs_merge() function. Co-developed-by: Jason Gunthorpe Signed-off-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 ++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 41 +++++++++++++++++++-- 2 files changed, 45 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index ed8820f12ba3..5e0e5055af1e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -928,6 +928,14 @@ struct arm_smmu_master { struct arm_smmu_device *smmu; struct device *dev; struct arm_smmu_stream *streams; + /* + * Scratch memory for a to_merge or to_unref array to build a per-domain + * invalidation array. It'll be pre-allocated with enough enries for all + * possible build scenarios. It can be used by only one caller at a time + * until the arm_smmu_invs_merge/unref() finishes. Must be locked by the + * iommu_group mutex. + */ + struct arm_smmu_invs *build_invs; struct arm_smmu_vmaster *vmaster; /* use smmu->streams_mutex */ /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 3f270c59f018..5a0a8b136352 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3784,12 +3784,22 @@ static int arm_smmu_init_sid_strtab(struct arm_smmu= _device *smmu, u32 sid) return 0; } =20 +static int arm_smmu_stream_id_cmp(const void *_l, const void *_r) +{ + const typeof_member(struct arm_smmu_stream, id) *l =3D _l; + const typeof_member(struct arm_smmu_stream, id) *r =3D _r; + + return cmp_int(*l, *r); +} + static int arm_smmu_insert_master(struct arm_smmu_device *smmu, struct arm_smmu_master *master) { int i; int ret =3D 0; struct iommu_fwspec *fwspec =3D dev_iommu_fwspec_get(master->dev); + bool ats_supported =3D dev_is_pci(master->dev) && + pci_ats_supported(to_pci_dev(master->dev)); =20 master->streams =3D kcalloc(fwspec->num_ids, sizeof(*master->streams), GFP_KERNEL); @@ -3797,14 +3807,35 @@ static int arm_smmu_insert_master(struct arm_smmu_d= evice *smmu, return -ENOMEM; master->num_streams =3D fwspec->num_ids; =20 - mutex_lock(&smmu->streams_mutex); + if (!ats_supported) { + /* Base case has 1 ASID entry or maximum 2 VMID entries */ + master->build_invs =3D arm_smmu_invs_alloc(2); + } else { + /* ATS case adds num_ids of entries, on top of the base case */ + master->build_invs =3D arm_smmu_invs_alloc(2 + fwspec->num_ids); + } + if (!master->build_invs) { + kfree(master->streams); + return -ENOMEM; + } + for (i =3D 0; i < fwspec->num_ids; i++) { struct arm_smmu_stream *new_stream =3D &master->streams[i]; - struct rb_node *existing; - u32 sid =3D fwspec->ids[i]; =20 - new_stream->id =3D sid; + new_stream->id =3D fwspec->ids[i]; new_stream->master =3D master; + } + + /* Put the ids into order for sorted to_merge/to_unref arrays */ + sort_nonatomic(master->streams, master->num_streams, + sizeof(master->streams[0]), arm_smmu_stream_id_cmp, + NULL); + + mutex_lock(&smmu->streams_mutex); + for (i =3D 0; i < fwspec->num_ids; i++) { + struct arm_smmu_stream *new_stream =3D &master->streams[i]; + struct rb_node *existing; + u32 sid =3D new_stream->id; =20 ret =3D arm_smmu_init_sid_strtab(smmu, sid); if (ret) @@ -3834,6 +3865,7 @@ static int arm_smmu_insert_master(struct arm_smmu_dev= ice *smmu, for (i--; i >=3D 0; i--) rb_erase(&master->streams[i].node, &smmu->streams); kfree(master->streams); + kfree(master->build_invs); } mutex_unlock(&smmu->streams_mutex); =20 @@ -3855,6 +3887,7 @@ static void arm_smmu_remove_master(struct arm_smmu_ma= ster *master) mutex_unlock(&smmu->streams_mutex); =20 kfree(master->streams); + kfree(master->build_invs); } =20 static struct iommu_device *arm_smmu_probe_device(struct device *dev) --=20 2.43.0