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AJvYcCVdZrRUKnEllQ7AoEZjde27xmeMuJn4rkuhp2+GK1Tl0Hy7eEWVwTeB4kvlmv19V4Q5zN3OJKMTiA5J@vger.kernel.org, AJvYcCXuB0NDgNvTckkYxlXsvG8hLiE796LXrT0ZgnCA/qjlD/DDIPtoapZkjFogKr+Igl1Rm4hvIn3pRlN0U9DX@vger.kernel.org X-Gm-Message-State: AOJu0YwdmpBFDPj1nioXKO+e7E6+xMTr+8lVJnSfo/9JZyFJMdYJnEjq n2IjmPiT53UQaHlDpjluEcIeSlcYvuuHmcY6mUfmopMxxoDjNB1h X-Google-Smtp-Source: AGHT+IExdqCVvtfANRWv9lUO362sv1gaRUggc3/UVeXpal0yMHNBYIFFnDgdeYQf/09eHGl1kDf7cg== X-Received: by 2002:a05:6871:7a9:b0:287:e3e1:15f2 with SMTP id 586e51a60fabf-295601585f1mr8943535fac.25.1731297705248; Sun, 10 Nov 2024 20:01:45 -0800 (PST) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-29546d0085csm2622580fac.22.2024.11.10.20.01.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 Nov 2024 20:01:44 -0800 (PST) From: Chen Wang To: u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, arnd@arndb.de, unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org, inochiama@outlook.com, krzk+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, tglx@linutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI Date: Mon, 11 Nov 2024 12:01:36 +0800 Message-Id: <5186bb9c7feebb87136eb5e5e117fb1142dba4c2.1731296803.git.unicorn_wang@outlook.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen Wang Add binding for Sophgo SG2042 MSI controller. Signed-off-by: Chen Wang --- .../sophgo,sg2042-msi.yaml | 78 +++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= sophgo,sg2042-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,= sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/so= phgo,sg2042-msi.yaml new file mode 100644 index 000000000000..9fe99b74c211 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-= msi.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 MSI Controller + +maintainers: + - Chen Wang + +description: + This interrupt controller is in Sophgo SG2042 for transforming interrupt= s from + PCIe MSI to PLIC interrupts. + +allOf: + - $ref: /schemas/interrupts.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: sophgo,sg2042-msi + + reg: + items: + - description: clear register + + reg-names: + items: + - const: clr + + sophgo,msi-doorbell-addr: + description: + u64 value of the MSI doorbell address + $ref: /schemas/types.yaml#/definitions/uint64 + + sophgo,msi-base-vec: + description: + u32 value of the base of parent PLIC vector allocated + to MSI. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 64 + maximum: 95 + + sophgo,msi-num-vecs: + description: + u32 value of the number of parent PLIC vectors allocated + to MSI. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 32 + + msi-controller: true + +required: + - compatible + - reg + - reg-names + - msi-controller + - sophgo,msi-doorbell-addr + - sophgo,msi-base-vec + - sophgo,msi-num-vecs + +additionalProperties: true + +examples: + - | + #include + msi: msi-controller@30000000 { + compatible =3D "sophgo,sg2042-msi"; + reg =3D <0x30000000 0x4>; + reg-names =3D "clr"; + msi-controller; + sophgo,msi-doorbell-addr =3D <0x00000070 0x30010300>; + sophgo,msi-base-vec =3D <64>; + sophgo,msi-num-vecs =3D <32>; + interrupt-parent =3D <&plic>; + }; --=20 2.34.1