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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF0002636A.mail.protection.outlook.com (10.167.241.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9203.9 via Frontend Transport; Mon, 6 Oct 2025 23:13:52 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Mon, 6 Oct 2025 16:13:50 -0700 From: Babu Moger To: , , , , , , , , CC: , , , , , Subject: [PATCH] x86/resctrl: Fix buggy overflow when reactivating previously Unavailable RMID Date: Mon, 6 Oct 2025 18:13:44 -0500 Message-ID: <515a38328989e48d403ef5a7d6dd321ba3343a61.1759791957.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2025 23:13:52.5255 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c2af85a4-cb8f-4745-7e72-08de052e03f0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4440 The issue was observed during testing on systems with multiple resctrl domains, where tasks were dynamically moved between domains. Users can create as many monitoring groups as the number of RMIDs supported by the hardware. However, on AMD systems, only a limited number of RMIDs are guaranteed to be actively tracked by the hardware. RMIDs that exceed this limit are placed in an "Unavailable" state. When an RMID transitions from "Unavailable" back to active, the hardware sets the IA32_QM_CTR.Unavailable (bit 62) on the first read from MSR_IA32_QM_CTR. This indicates that the RMID was not previously tracked. Once the hardware begins tracking the RMID, subsequent reads from that RMID will have the Unavailable bit cleared, as long as it remains tracked. Problem scenario: 1. The resctrl filesystem is mounted, and a task is assigned to a monitoring group. $mount -t resctrl resctr /sys/fs/resctrl $mkdir /sys/fs/resctr/mon_groups/test1 $echo 1234 > /sys/fs/resctrl/mon_groups/test1/tasks $cat /sys/fs/resctrl/mon_groups/test1/mon_data/l3_mon_*/mbm_total_bytes 21323 <- Total bytes on domain 0 "Unavailable" <- Total bytes on domain 1 Task is running on domain 0. Counter on domain 1 is "Unavailable". 2. The task runs on domain 0 for a while and then moves to domain 1. The counter starts incrementing on domain 1. $cat /sys/fs/resctrl/mon_groups/mon_data/l3_mon_*/mbm_total_bytes 7345357 <- Total bytes on domain 0 4545 <- Total bytes on domain 1 3. At some point, the RMID in domain 0 transitions to the "Unavailable" state because the task is no longer executing in that domain. $cat /sys/fs/resctrl/mon_groups/mon_data/l3_mon_*/mbm_total_bytes "Unavailable" <- Total bytes on domain 0 434341 <- Total bytes on domain 1 4. Since the task continues to migrate between domains, it may eventually return to domain 0. $cat /sys/fs/resctrl/mon_groups/mon_data/l3_mon_*/mbm_total_bytes 17592178699059 <- Overflow on domain 0 3232332 <- Total bytes on domain 1 Because the RMID transitions from the =E2=80=9CUnavailable=E2=80=9D sta= te to the active state, the first read sets IA32_QM_CTR.Unavailable (bit 62). The following read starts counting from zero, which can be lower than the previously saved MSR value (7345357). Consequently, the kernel=E2= =80=99s overflow logic is triggered=E2=80=94it compares the previous value (734= 5357) with the new, smaller value and mistakenly interprets this as a counter overflow, adding a large delta. In reality, this is a false positive: the counter didn=E2=80=99t overflow but was simply reset when the RMID transitioned from =E2=80=9CUnavailable=E2=80=9D back to active. Fix the issue by resetting the prev_msr value to zero when hardware returns IA32_QM_CTR.Unavailable (bit 62) when the RMID becomes active from "Unavailable". Here is the text from APM [1]. "In PQOS Version 2.0 or higher, the MBM hardware will set the U bit on the first QM_CTR read when it begins tracking an RMID that it was not previously tracking. The U bit will be zero for all subsequent reads from that RMID while it is still tracked by the hardware. Therefore, a QM_CTR read with the U bit set when that RMID is in use by a processor can be considered 0 when calculating the difference with a subsequent read." The details are documented in APM [1] available from [2]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3 Monitoring L3 Memory Bandwidth (MBM). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 # [2] --- Tested this on multiple AMD systems, but not on Intel systems. Need help with that. If everything goes well, this patch needs to go to all the stable kernels. --- arch/x86/kernel/cpu/resctrl/monitor.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index c8945610d455..a685370dd160 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -242,7 +242,9 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, stru= ct rdt_mon_domain *d, u32 unused, u32 rmid, enum resctrl_event_id eventid, u64 *val, void *ignored) { + struct rdt_hw_mon_domain *hw_dom =3D resctrl_to_arch_mon_dom(d); int cpu =3D cpumask_any(&d->hdr.cpu_mask); + struct arch_mbm_state *am; u64 msr_val; u32 prmid; int ret; @@ -251,12 +253,21 @@ int resctrl_arch_rmid_read(struct rdt_resource *r, st= ruct rdt_mon_domain *d, =20 prmid =3D logical_rmid_to_physical_rmid(cpu, rmid); ret =3D __rmid_read_phys(prmid, eventid, &msr_val); - if (ret) - return ret; =20 - *val =3D get_corrected_val(r, d, rmid, eventid, msr_val); + switch (ret) { + case 0: + *val =3D get_corrected_val(r, d, rmid, eventid, msr_val); + break; + case -EINVAL: + am =3D get_arch_mbm_state(hw_dom, rmid, eventid); + if (am) + am->prev_msr =3D 0; + break; + default: + break; + } =20 - return 0; + return ret; } =20 static int __cntr_id_read(u32 cntr_id, u64 *val) --=20 2.34.1