From nobody Mon Feb 9 21:11:54 2026 Received: from mail-244122.protonmail.ch (mail-244122.protonmail.ch [109.224.244.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5766534EF0D for ; Mon, 12 Jan 2026 17:28:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.122 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768238912; cv=none; b=JmMSO06ZtPozFg2gYPo6w9TnHnaZAfQz5DvUx0ZY7lQiZ0BIc8nUT0o/gU8xjSUt2RKRame4+E6ii8L7OLFfkLF2Xbk6tF4QNJNp5OtI2GmbEanWbP26Bdc/PF/Jxjg/Zxd5KwLhq5Ac3tElaTQ1ibbDBNugMpTRDoJalhs3Ea0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768238912; c=relaxed/simple; bh=cLU1yDlyIufiMciF88eGTnMUwfesXy9yINZ4eeqk2+I=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JbpYa1RHS3rP9xWyKHlpUEUVERS7KfcISJT1zBzliLg950UMEBfEAGExV8g8dgNVwnRiw9049KnYM6U6LXcXCzX8LdoVEPKeMoKtj1Wc25VkZtG6JAKVBDkD2SghE4g60KhWK9KydYE5Zjc0n795ZX58Wnt6o45tX31geCpPhNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=bI4dr47+; arc=none smtp.client-ip=109.224.244.122 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="bI4dr47+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1768238898; x=1768498098; bh=tF6uZeqRtsc0uhEqsykdQtAU19tdI7CeSMEK1HyPxRA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=bI4dr47+xRCLvtcsrhtgqXqw2ZjCjbd2gZQ6cVMPKcNGuo1WJHUcJI/jkmKU4lcyg pG7F82zV/I2yyJP4eQyRRkzVbuzOk54izHwiIqO41dOI/ap4FoVG2+ORE5Z39H0wZk TmnmNZ76D/nrR+aZWj8Tv6tPVb5y8LAIJJAd7cnwQPIDHhqkD/sRl/e43XZ1Nss18l idBOQvCCKRSo2nQ7EG3BpmE6CjnNFZYD38dkAVjlqduYm7PqZEx+Kwazrv0aZF3N3J u9SI6l780MyFBed/IRpJrWR52k6pqTKkSbnCVLJm2qyMaL7ei/PYPnm0+kouzTtj3z pTv/y+lqw6j+g== Date: Mon, 12 Jan 2026 17:28:14 +0000 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Maciej Wieczor-Retman , Alexander Potapenko , linux-kernel@vger.kernel.org Subject: [PATCH v8 10/14] x86/mm: LAM initialization Message-ID: <4ff09ec1753ea22798eb323584c42c1b531795e6.1768233085.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: 5af161bc566890375aff104786603ef8f466963e Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman To make use of KASAN's tag based mode on x86, Linear Address Masking (LAM) needs to be enabled. To do that the 28th bit in CR4 has to be set. Set the bit in early memory initialization. When launching secondary CPUs the LAM bit gets lost. To avoid this add it in a mask in head_64.S. The bitmask permits some bits of CR4 to pass from the primary CPU to the secondary CPUs without being cleared. Signed-off-by: Maciej Wieczor-Retman Acked-by: Alexander Potapenko --- Changelog v7: - Add Alexander's acked-by tag. Changelog v6: - boot_cpu_has() -> cpu_feature_enabled() arch/x86/kernel/head_64.S | 3 +++ arch/x86/mm/init.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 21816b48537c..c5a0bfbe280d 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -209,6 +209,9 @@ SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL) * there will be no global TLB entries after the execution." */ movl $(X86_CR4_PAE | X86_CR4_LA57), %edx +#ifdef CONFIG_ADDRESS_MASKING + orl $X86_CR4_LAM_SUP, %edx +#endif #ifdef CONFIG_X86_MCE /* * Preserve CR4.MCE if the kernel will enable #MC support. diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 8bf6ad4b9400..a8442b255481 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -764,6 +764,9 @@ void __init init_mem_mapping(void) probe_page_size_mask(); setup_pcid(); =20 + if (cpu_feature_enabled(X86_FEATURE_LAM) && IS_ENABLED(CONFIG_KASAN_SW_TA= GS)) + cr4_set_bits_and_update_boot(X86_CR4_LAM_SUP); + #ifdef CONFIG_X86_64 end =3D max_pfn << PAGE_SHIFT; #else --=20 2.52.0