From nobody Tue Dec 16 19:54:51 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5F47C7EE2C for ; Thu, 24 Aug 2023 07:16:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240312AbjHXHP7 (ORCPT ); Thu, 24 Aug 2023 03:15:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240379AbjHXHPk (ORCPT ); Thu, 24 Aug 2023 03:15:40 -0400 Received: from jari.cn (unknown [218.92.28.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3F1461996 for ; Thu, 24 Aug 2023 00:15:05 -0700 (PDT) Received: from chenxuebing$jari.cn ( [125.70.163.142] ) by ajax-webmail-localhost.localdomain (Coremail) ; Thu, 24 Aug 2023 15:14:39 +0800 (GMT+08:00) X-Originating-IP: [125.70.163.142] Date: Thu, 24 Aug 2023 15:14:39 +0800 (GMT+08:00) X-CM-HeaderCharset: UTF-8 From: "XueBing Chen" To: alexander.deucher@amd.com, airlied@gmail.com, daniel@ffwll.ch Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/amdgpu: Clean up errors in dce_v11_0.c X-Priority: 3 X-Mailer: Coremail Webmail Server Version 2023.1-cmXT6 build 20230419(ff23bf83) Copyright (c) 2002-2023 www.mailtech.cn mispb-4e503810-ca60-4ec8-a188-7102c18937cf-zhkzyfz.cn Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Message-ID: <4e7007e6.63e.18a26652d06.Coremail.chenxuebing@jari.cn> X-Coremail-Locale: zh_CN X-CM-TRANSID: AQAAfwD3lD9fA+dkYTSSAA--.484W X-CM-SenderInfo: hfkh05pxhex0nj6mt2flof0/1tbiAQANCmTl1A4AOgAKst X-Coremail-Antispam: 1Ur529EdanIXcx71UUUUU7IcSsGvfJ3iIAIbVAYjsxI4VWxJw CS07vEb4IE77IF4wCS07vE1I0E4x80FVAKz4kxMIAIbVAFxVCaYxvI4VCIwcAKzIAtYxBI daVFxhVjvjDU= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Fix the following errors reported by checkpatch: ERROR: that open brace { should be on the previous line ERROR: switch and case should be at the same indent ERROR: space required before the open parenthesis '(' ERROR: space required before the open brace '{' Signed-off-by: XueBing Chen --- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 20 ++++++++------------ 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/a= mdgpu/dce_v11_0.c index c14b70350a51..cb630dfdcd50 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1451,8 +1451,7 @@ static void dce_v11_0_audio_enable(struct amdgpu_devi= ce *adev, enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED= _MASK : 0); } =20 -static const u32 pin_offsets[] =3D -{ +static const u32 pin_offsets[] =3D { AUD0_REGISTER_OFFSET, AUD1_REGISTER_OFFSET, AUD2_REGISTER_OFFSET, @@ -1853,8 +1852,7 @@ static void dce_v11_0_afmt_fini(struct amdgpu_device = *adev) } } =20 -static const u32 vga_control_regs[6] =3D -{ +static const u32 vga_control_regs[6] =3D { mmD1VGA_CONTROL, mmD2VGA_CONTROL, mmD3VGA_CONTROL, @@ -3240,7 +3238,7 @@ static int dce_v11_0_set_crtc_irq_state(struct amdgpu= _device *adev, case AMDGPU_CRTC_IRQ_VLINE5: dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); break; - case AMDGPU_CRTC_IRQ_VLINE6: + case AMDGPU_CRTC_IRQ_VLINE6: dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); break; default: @@ -3295,12 +3293,12 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_dev= ice *adev, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); =20 /* IRQ could occur when in initial stage */ - if(amdgpu_crtc =3D=3D NULL) + if (amdgpu_crtc =3D=3D NULL) return 0; =20 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); works =3D amdgpu_crtc->pflip_works; - if (amdgpu_crtc->pflip_status !=3D AMDGPU_FLIP_SUBMITTED){ + if (amdgpu_crtc->pflip_status !=3D AMDGPU_FLIP_SUBMITTED) { DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status =3D %d !=3D " "AMDGPU_FLIP_SUBMITTED(%d)\n", amdgpu_crtc->pflip_status, @@ -3314,7 +3312,7 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_devic= e *adev, amdgpu_crtc->pflip_works =3D NULL; =20 /* wakeup usersapce */ - if(works->event) + if (works->event) drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); =20 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); @@ -3780,8 +3778,7 @@ static void dce_v11_0_set_irq_funcs(struct amdgpu_dev= ice *adev) adev->hpd_irq.funcs =3D &dce_v11_0_hpd_irq_funcs; } =20 -const struct amdgpu_ip_block_version dce_v11_0_ip_block =3D -{ +const struct amdgpu_ip_block_version dce_v11_0_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_DCE, .major =3D 11, .minor =3D 0, @@ -3789,8 +3786,7 @@ const struct amdgpu_ip_block_version dce_v11_0_ip_blo= ck =3D .funcs =3D &dce_v11_0_ip_funcs, }; =20 -const struct amdgpu_ip_block_version dce_v11_2_ip_block =3D -{ +const struct amdgpu_ip_block_version dce_v11_2_ip_block =3D { .type =3D AMD_IP_BLOCK_TYPE_DCE, .major =3D 11, .minor =3D 2, --=20 2.17.1