From nobody Wed Feb 11 06:31:20 2026 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 35E1624C667; Mon, 10 Feb 2025 21:14:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222059; cv=none; b=He7ZrJ+IJywMWxuW8aui1F8tbuKZKwBc1Hyzwaj3Wg/k+Q988ozl+KdOh1qhuEUIOjeIzZ9coMwIh6Q1IBsphydO18GaQIhS0iyNjNgxI5e7FKsjVt2rqrOGzHAXZXLDlKGyiQYZfavKMePyGAx1jK6pgeAlb0OcinqzC435PoY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739222059; c=relaxed/simple; bh=EC1+VWxeTyKipOmsfV+ugr3Ogr25ipgQiLkDdijoRG8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=hk/WNpPQYgIAzUnz6hBe6gHM7ZKRVl7MuvhOhOfPjz/lRPnYFyqgrensxz2BK8MGipIE9Jcx1nNEc9WTEoT6iJa/uTsrPWWyoSW5xOOYIi6nd9NpenT8T3QIBryjo5FGyKWE3wmaF3HLBFW1+Hu+v8uUJ0JtIIlHN49nbYhYgzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=pNo0CyUI; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="pNo0CyUI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1739222057; x=1770758057; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EC1+VWxeTyKipOmsfV+ugr3Ogr25ipgQiLkDdijoRG8=; b=pNo0CyUIGpry6AtIuS+DDwY9qR/LfWnxHaLGLx/ebx9YavdVDuJbODc6 QJcDKuR8oruPQB59XtPF1nbX1aGbGKwhYoONsZUNiuv3Vxdjt1vP7ZV9A mIR+vZ8DTACtsYt6TuQD+ScI9tGzupTr1lIU1d7v4ZqLuJPyySaZGIPhH PdU/ZAnlpWEK4gHthFxTOCUQorkTx/xczhhx7TsC0zInJNj66hwSqx4VU AI1VWko+yzW1mD8ACt1CChGPD82RUGAlf1eurJ2y33d35diowwvQg67RP /xIgXtDLT4jNM706O4F7nBw0go58Fk0DB8qnEmqi7bBo1xL5cvI1r4jAG w==; X-CSE-ConnectionGUID: AYqW9AG9RbOJ2Xf8Pt97Yw== X-CSE-MsgGUID: 1dErltO1Rla3Z/Bsv54o7g== X-IronPort-AV: E=Sophos;i="6.13,275,1732604400"; d="scan'208";a="205027983" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 10 Feb 2025 14:14:06 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 10 Feb 2025 14:13:46 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 10 Feb 2025 14:13:46 -0700 From: To: , , , , , , , , CC: , , , , , , Li Bin , Ryan Wanner , "Durai Manickam KR" , Andrei Simion Subject: [PATCH v2 09/15] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration Date: Mon, 10 Feb 2025 14:13:09 -0700 Message-ID: <4e685b1f1828b006cb60aa6b66239f2c0966501a.1739221064.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Li Bin For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error" during recalibrating the impedance in BootStrap. We found that the impedance value saved in at91_suspend_finish() before the DDR entered self-refresh mode did not match the resistor values. The ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to select the different impedance setting. But these gray code are incorrect, a workaournd from design team fixed the bug in the calibration logic. The ZDATA contains four independent impedance elements, but the algorithm combined the four elements into one. The elemen= ts were fixed using properly shifted offsets. Signed-off-by: Li Bin [nicolas.ferre@microchip.com: fix indentation and combine 2 patches] Signed-off-by: Nicolas Ferre Tested-by: Ryan Wanner Tested-by: Durai Manickam KR Tested-by: Andrei Simion --- arch/arm/mach-at91/pm.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 05a1547642b60..6c3e6aa22606f 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz; =20 static int at91_suspend_finish(unsigned long val) { - unsigned char modified_gray_code[] =3D { - 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d, - 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b, - 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, - 0x10, 0x11, + /* SYNOPSYS workaround to fix a bug in the calibration logic */ + unsigned char modified_fix_code[] =3D { + 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18, + 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13, + 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14, + 0x1e, 0x1f, }; unsigned int tmp, index; int i; @@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val) * restore the ZQ0SR0 with the value saved here. But the * calibration is buggy and restoring some values from ZQ0SR0 * is forbidden and risky thus we need to provide processed - * values for these (modified gray code values). + * values for these. */ tmp =3D readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0); =20 /* Store pull-down output impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] =3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] =3D modified_fix_code[index] << DDR3PH= Y_ZQ0SR0_PDO_OFF; =20 /* Store pull-up output impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_fix_code[index] << DDR3P= HY_ZQ0SR0_PUO_OFF; =20 /* Store pull-down on-die termination impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_fix_code[index] << DDR3P= HY_ZQ0SR0_PDODT_OFF; =20 /* Store pull-up on-die termination impedance select. */ index =3D (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f; - soc_pm.bu->ddr_phy_calibration[0] |=3D modified_gray_code[index]; + soc_pm.bu->ddr_phy_calibration[0] |=3D modified_fix_code[index] << DDR3P= HY_ZQ0SRO_PUODT_OFF; =20 /* * The 1st 8 words of memory might get corrupted in the process --=20 2.43.0