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Tue, 04 Nov 2025 21:55:24 -0800 (PST) Received: from geday ([2804:7f2:800b:2cb7::dead:c001]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7c6c2448c76sm1714476a34.2.2025.11.04.21.55.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Nov 2025 21:55:23 -0800 (PST) Date: Wed, 5 Nov 2025 02:55:10 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Conor Dooley , Johan Jonker , Geraldo Nascimento Subject: [PATCH] arm64: dts: rockchip: align bindings to PCIe spec Message-ID: <4b5ffcccfef2a61838aa563521672a171acb27b2.1762321976.git.geraldogabriel@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The PERST# side-band signal is defined by PCIe spec as an open-drain active-low signal that depends on a pull-up resistor to keep the signal high when deasserted. Align bindings to the spec. Note that the relevant driver hacks the active-low signal as active-high and switches the normal polarity of PERST# assertion/deassertion, 1 and 0 in that order, and instead uses 0 to signal low (assertion) and 1 to signal deassertion. Incidentally, this change makes hardware that refused to work with the Rockchip-IP PCIe core working for me, which was the object of many fool's errands. Signed-off-by: Geraldo Nascimento --- arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/a= rm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi index aa70776e898a..8dcb03708145 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi @@ -383,9 +383,9 @@ &pcie_phy { }; =20 &pcie0 { - ep-gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + ep-gpios =3D <&gpio0 RK_PB4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; num-lanes =3D <4>; - pinctrl-0 =3D <&pcie_clkreqnb_cpm>; + pinctrl-0 =3D <&pcie_clkreqnb_cpm>, <&pcie_perst>; pinctrl-names =3D "default"; vpcie0v9-supply =3D <&vcca_0v9>; /* VCC_0V9_S0 */ vpcie1v8-supply =3D <&vcca_1v8>; /* VCC_1V8_S0 */ @@ -408,6 +408,10 @@ pcie { pcie_pwr: pcie-pwr { rockchip,pins =3D <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; + pcie_perst: pcie-perst { + rockchip,pins =3D <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; =20 pmic { --=20 2.49.0