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[188.152.100.94]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4839731d7c3sm1096185e9.18.2026.02.17.10.43.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Feb 2026 10:43:34 -0800 (PST) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Subject: [PATCH v1 08/11] arm64: dts: imx8mm-var-som-symphony: Enable uSD on USDHC2 Date: Tue, 17 Feb 2026 19:42:42 +0100 Message-ID: <4b23da4592f50a49009fa59e45fbdc12d277eef9.1771353301.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Enable the microSD slot on the VAR-SOM Symphony carrier board. Configure USDHC2 with card-detect GPIO, pinctrl states for the supported bus speeds and the required VMMC supply. Update the VMMC regulator to match the latest carrier revision by moving the enable GPIO to GPIO4_IO22 and adding the required off-on delay. Signed-off-by: Stefano Radaelli --- .../dts/freescale/imx8mm-var-som-symphony.dts | 59 ++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts index 3242a0b739f6..40ffa1f36b2f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-som-symphony.dts @@ -22,7 +22,8 @@ reg_usdhc2_vmmc: regulator-usdhc2-vmmc { regulator-name =3D "VSD_3V3"; regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; - gpio =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + gpio =3D <&gpio4 22 GPIO_ACTIVE_HIGH>; + off-on-delay-us =3D <20000>; enable-active-high; }; =20 @@ -204,6 +205,18 @@ &usbotg2 { status =3D "okay"; }; =20 +/* SD */ +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios =3D <&gpio1 10 GPIO_ACTIVE_LOW>; + vmmc-supply =3D <®_usdhc2_vmmc>; + bus-width =3D <4>; + status =3D "okay"; +}; + &pinctrl_fec1 { fsl,pins =3D < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -264,7 +277,7 @@ MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x120 =20 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins =3D < - MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41 >; }; =20 @@ -288,4 +301,46 @@ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 >; }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc1 + >; + }; }; --=20 2.47.3