From nobody Wed Dec 17 00:00:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13C87ECAAD5 for ; Mon, 5 Sep 2022 07:55:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237001AbiIEHzN (ORCPT ); Mon, 5 Sep 2022 03:55:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236396AbiIEHzJ (ORCPT ); Mon, 5 Sep 2022 03:55:09 -0400 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F060175B1 for ; Mon, 5 Sep 2022 00:55:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1662364501; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AdS8+B/O/n4mduTrHxo0RL4fuHx8wGK9eiouBtBzHLE=; b=nq/Sz1Z7EABiXwAHZKYqd+Carge9I9yVZMSrZasFXAw5iMpT+xL9kqBYBTKsCI8emXOaRC 5xCEosXDh7yh+gs1cEXpOuWwwHrKFYVAY/VyKrZCrCRA2eLG1YteZC6HSimHW+M8hkzSoT hfnEk80xbK9/LKXf3idMg72/DBI7bOunHmfFZI/80nEZLEEApsMvcIWLzYISLffCKGyhvo 3DfhZzTTcIsXS4yYs39KKDk5D1fQ9GzRkypE9APQ5big6pfaA2eSxVsvYB6ckwU6IBBjSm IZzeUfz8NuF28TcUzgFk4FX4zQtHEFz3FUG2SYjl4bc6r56As52GzF5VbngPNw== Received: from mail.maxlinear.com (174-47-1-83.static.ctl.one [174.47.1.83]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-354-xdhXJq8hOTmBhXYhWCcCPw-1; Mon, 05 Sep 2022 03:44:03 -0400 X-MC-Unique: xdhXJq8hOTmBhXYhWCcCPw-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.120) with Microsoft SMTP Server id 15.1.2375.24; Mon, 5 Sep 2022 00:43:59 -0700 From: Rahul Tanwar To: , , CC: , , "Rahul Tanwar" Subject: [PATCH v2 3/5] clk: mxl: Avoid disabling gate clocks from clk driver Date: Mon, 5 Sep 2022 15:43:46 +0800 Message-ID: <496372f326760be1b997ae2aabd1999627f7376d.1662363020.git.rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In MxL's LGM SoC, gate clocks are supposed to be enabled or disabled from EPU (power management IP) in certain power saving modes. If gate clocks are allowed to be enabled/disabled from CGU clk driver, then there arises a conflict where in case clk driver disables a gate clk, and then EPU tries to disable the same gate clk, then it will hang polling for the clk gated successful status. To avoid such a conflict, disable gate clocks enabling/disabling from CGU clk driver. But add a GATE_CLK_HW flag to control this in order to be backward compatible with other SoCs which share the same CGU IP but not the same EPU IP. Signed-off-by: Rahul Tanwar --- drivers/clk/x86/clk-cgu.c | 32 ++++++++++++++++++++++++-------- drivers/clk/x86/clk-cgu.h | 1 + 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c index 1f7e93de67bc..d24173cfe0b0 100644 --- a/drivers/clk/x86/clk-cgu.c +++ b/drivers/clk/x86/clk-cgu.c @@ -258,8 +258,12 @@ static int lgm_clk_gate_enable(struct clk_hw *hw) struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); unsigned int reg; =20 - reg =3D GATE_HW_REG_EN(gate->reg); - lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); + if (gate->flags & GATE_CLK_HW) { + reg =3D GATE_HW_REG_EN(gate->reg); + lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); + } else { + gate->reg =3D 1; + } =20 return 0; } @@ -269,8 +273,12 @@ static void lgm_clk_gate_disable(struct clk_hw *hw) struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); unsigned int reg; =20 - reg =3D GATE_HW_REG_DIS(gate->reg); - lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); + if (gate->flags & GATE_CLK_HW) { + reg =3D GATE_HW_REG_DIS(gate->reg); + lgm_set_clk_val(gate->membase, reg, gate->shift, 1, 1); + } else { + gate->reg =3D 0; + } } =20 static int lgm_clk_gate_is_enabled(struct clk_hw *hw) @@ -278,8 +286,12 @@ static int lgm_clk_gate_is_enabled(struct clk_hw *hw) struct lgm_clk_gate *gate =3D to_lgm_clk_gate(hw); unsigned int reg, ret; =20 - reg =3D GATE_HW_REG_STAT(gate->reg); - ret =3D lgm_get_clk_val(gate->membase, reg, gate->shift, 1); + if (gate->flags & GATE_CLK_HW) { + reg =3D GATE_HW_REG_STAT(gate->reg); + ret =3D lgm_get_clk_val(gate->membase, reg, gate->shift, 1); + } else { + ret =3D gate->reg; + } =20 return ret; } @@ -315,7 +327,8 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx, init.num_parents =3D pname ? 1 : 0; =20 gate->membase =3D ctx->membase; - gate->reg =3D reg; + if (cflags & GATE_CLK_HW) + gate->reg =3D reg; gate->shift =3D shift; gate->flags =3D cflags; gate->hw.init =3D &init; @@ -326,7 +339,10 @@ lgm_clk_register_gate(struct lgm_clk_provider *ctx, return ERR_PTR(ret); =20 if (cflags & CLOCK_FLAG_VAL_INIT) { - lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val); + if (cflags & GATE_CLK_HW) + lgm_set_clk_val(gate->membase, reg, shift, 1, list->gate_val); + else + gate->reg =3D 1; } =20 return hw; diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h index 0aa0f35d63a0..73ce84345f81 100644 --- a/drivers/clk/x86/clk-cgu.h +++ b/drivers/clk/x86/clk-cgu.h @@ -197,6 +197,7 @@ struct lgm_clk_branch { /* clock flags definition */ #define CLOCK_FLAG_VAL_INIT BIT(16) #define MUX_CLK_SW BIT(17) +#define GATE_CLK_HW BIT(18) =20 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ _shift, _width, _cf, _v) \ --=20 2.17.1