From nobody Sat Oct 4 01:44:59 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 096723451DE; Thu, 21 Aug 2025 18:23:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800620; cv=none; b=d3MUpPTSSlH9puIePc5l1lEOLGslzF+bF7qiGEseEpdeTAj1TZZIpQg6Oq+aDy4V/5dy3zmmH4/H9f5etBr6OUWPdgfU1aCYYVptWmq3l6wRDfR6Yb4M34Z44jtXF6ogZXSvrrisxHzJdrpvkRe2tkKqUrLQwnOF75QU/21Ip18= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755800620; c=relaxed/simple; bh=+bsXqjrbjdk0kUQXXL1WrzIRuzrIEx7IY5OrHK70vXo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ovMqvYNa9u49jwYpkmIdO3In/Q10aDJ5uAUCu2UizJvcWMHa+s4YP6EiYDEuIZ9UjrKZIVjzZDGQ01XzAInvJM79Uf/uL1hUg8+mFFlCnAkBU+lkv8hALvBntUQfR2/MsUu+SbW52vqBmQ/t7k6j5/qNPy6sHRDp7Be73OE1QsE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gXOFFeCL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gXOFFeCL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EB229C4CEEB; Thu, 21 Aug 2025 18:23:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755800618; bh=+bsXqjrbjdk0kUQXXL1WrzIRuzrIEx7IY5OrHK70vXo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gXOFFeCLTTNqCVCKZ0JTD61qLiaW/lEaolroVnAs/+nklhVjQCH/tfdoABvL2Qzv+ ezddI3EL4PH5IYkaB4Dx/bUpNXhbrHBGkmVFCzivk00BPFClyCQSFV/X+9Dg8z/dgK hd0cfxb2J6VdDHtG+Cb3JfrxJlukh/xBA6XgX8Ue1VPqs/n4J0CmZ0CK0J2J1JPQ/r hxvemuevxPO/8q8eHt9NreQ8rErznyJB6oEVThnsKxlugPvnoPKPf4uiHArzjrjXs1 KZHNFdBDFYPg7G//Z0fCCva1J4KqY6olsoqdx9HKLEiQOsBUsbavKcdcHoOP2dcWbh 0lgV+g6o+tJKw== From: "Naveen N Rao (AMD)" To: Sean Christopherson , Paolo Bonzini Cc: , , Suravee Suthikulpanit , Vasant Hegde , Pankaj Gupta , Alejandro Jimenez , Joao Martins , Nikunj A Dadhania Subject: [PATCH v4 1/7] KVM: SVM: Limit AVIC physical max index based on configured max_vcpu_ids Date: Thu, 21 Aug 2025 23:48:32 +0530 Message-ID: <471e9725e5f10a4d609910c684152de4689c09f2.1755797611.git.naveen@kernel.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" KVM allows VMMs to specify the maximum possible APIC ID for a virtual machine through KVM_CAP_MAX_VCPU_ID capability so as to limit data structures related to APIC/x2APIC. Utilize the same to set the AVIC physical max index in the VMCB, similar to VMX. This helps hardware limit the number of entries to be scanned in the physical APIC ID table speeding up IPI broadcasts for virtual machines with smaller number of vCPUs. Unlike VMX, SVM AVIC requires a single page to be allocated for the Physical APIC ID table and the Logical APIC ID table, so retain the existing approach of allocating those during VM init. Signed-off-by: Naveen N Rao (AMD) --- arch/x86/kvm/svm/avic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index a34c5c3b164e..a6908ac5298d 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -82,6 +82,7 @@ bool x2avic_enabled; static void avic_activate_vmcb(struct vcpu_svm *svm) { struct vmcb *vmcb =3D svm->vmcb01.ptr; + struct kvm *kvm =3D svm->vcpu.kvm; =20 vmcb->control.int_ctl &=3D ~(AVIC_ENABLE_MASK | X2APIC_MODE_MASK); vmcb->control.avic_physical_id &=3D ~AVIC_PHYSICAL_MAX_INDEX_MASK; @@ -97,7 +98,8 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) */ if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { vmcb->control.int_ctl |=3D X2APIC_MODE_MASK; - vmcb->control.avic_physical_id |=3D X2AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |=3D min(kvm->arch.max_vcpu_ids - 1, + X2AVIC_MAX_PHYSICAL_ID); /* Disabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, false); } else { @@ -108,7 +110,8 @@ static void avic_activate_vmcb(struct vcpu_svm *svm) kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, &svm->vcpu); =20 /* For xAVIC and hybrid-xAVIC modes */ - vmcb->control.avic_physical_id |=3D AVIC_MAX_PHYSICAL_ID; + vmcb->control.avic_physical_id |=3D min(kvm->arch.max_vcpu_ids - 1, + AVIC_MAX_PHYSICAL_ID); /* Enabling MSR intercept for x2APIC registers */ svm_set_x2apic_msr_interception(svm, true); } --=20 2.50.1