From nobody Wed Oct 8 22:33:19 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 827F22D9EFF; Tue, 24 Jun 2025 15:08:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777735; cv=none; b=cM3HUmve3i5TNUWxMVcRz7WQaL3RsKRTeiW6HbFCRi/jzLUdLGXpy9BbpUpD/kWapJ3XaISx+lGnjpYYMhg/yp6XkqzZnk//r0SsPagasGaqnty5HGtgfRPkMDu6sQK7GbJKsiech9U1lqjoaBa9oJzq1xH/se2gLo83k01OeiU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750777735; c=relaxed/simple; bh=IOmmE+u6QTHG7zImgwkpWUVJQIDMRXSw76pKyrmRpPE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e18807LD3rUp8FFabovjE4tNhIEvpFoXw03H+sh2xOgQxN/WxIVmHKnJnnbf8LF01HUPmxeFKRctPupwr8zf1kBJBow5xTSXb+Ht0Zbm4oG4HjZWBCTC9k2qfpUIKgYsG+ttCp/V0mAq3BVD9Cozkmp6pE21w42DTJtj4B4KNu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Y/Pe3NGj; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Y/Pe3NGj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1750777733; x=1782313733; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IOmmE+u6QTHG7zImgwkpWUVJQIDMRXSw76pKyrmRpPE=; b=Y/Pe3NGjS0wlVMOvomGCdpCrh9nJq32t5J+s5O6eP8UdsQVJq2up/l80 GXr9ZNCNbTgHMX2q5cexFmrTnXfBbuesPiAUO2VcZvMwfdSpEghfflwYo V+YL27B4M66hQGqVpTK2GfwD2HfXTS2gOPrAf1vfZ32oXWGFTLWdSkLM/ qKFEZTMfFnyDrHZnW8nh2XtFPvnXHm48Un9/RnCoqMJl7GqfBKztYdl3M CkkR++z1nRBVd9DGg+bRpnlgcGsW4KteDoztIJlzqJ27CsxzAH+1AQ0KB DGsN7tY6I1wziRa97BVLIyJaGQglFJfuhcf9V3uz1a8uEmXQuddB5oUeR g==; X-CSE-ConnectionGUID: 4+RzxTN1Qsa6vG3Bpty4nA== X-CSE-MsgGUID: sq55A1TYTk+js9keUGKarA== X-IronPort-AV: E=Sophos;i="6.16,262,1744095600"; d="scan'208";a="42688187" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 24 Jun 2025 08:08:47 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Tue, 24 Jun 2025 08:08:37 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.44 via Frontend Transport; Tue, 24 Jun 2025 08:08:37 -0700 From: To: , , , , CC: , , , , Subject: [PATCH v2 12/32] clk: at91: clk-pll: add support for parent_hw Date: Tue, 24 Jun 2025 08:08:09 -0700 Message-ID: <46b968a38e722af2fbe6f2f4219add67323f05b9.1750182562.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for parent_hw in pll clock driver. With this parent-child relation is described with pointers rather than strings making registration a bit faster. All the SoC based drivers that rely on clk-pll were adapted to the new API change. The switch itself for SoCs will be done in subsequent patches. Signed-off-by: Claudiu Beznea [ryan.wanner@microchip.com: Remove SoC specific changes as they are going to be coalesced into one SoC specific commit.] Signed-off-by: Ryan Wanner --- drivers/clk/at91/clk-pll.c | 9 ++++++--- drivers/clk/at91/dt-compat.c | 2 +- drivers/clk/at91/pmc.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c index 249d6a53cedf..f973c3b1bbec 100644 --- a/drivers/clk/at91/clk-pll.c +++ b/drivers/clk/at91/clk-pll.c @@ -310,13 +310,13 @@ static const struct clk_ops pll_ops =3D { =20 struct clk_hw * __init at91_clk_register_pll(struct regmap *regmap, const char *name, - const char *parent_name, u8 id, + const char *parent_name, struct clk_parent_data *parent_data, u8 i= d, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics) { struct clk_pll *pll; struct clk_hw *hw; - struct clk_init_data init; + struct clk_init_data init =3D {}; int offset =3D PLL_REG(id); unsigned int pllr; int ret; @@ -330,7 +330,10 @@ at91_clk_register_pll(struct regmap *regmap, const cha= r *name, =20 init.name =3D name; init.ops =3D &pll_ops; - init.parent_names =3D &parent_name; + if (parent_data) + init.parent_data =3D (const struct clk_parent_data *)parent_data; + else + init.parent_names =3D &parent_name; init.num_parents =3D 1; init.flags =3D CLK_SET_RATE_GATE; =20 diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c index 7883198f6a98..2c5faa3b1cfd 100644 --- a/drivers/clk/at91/dt-compat.c +++ b/drivers/clk/at91/dt-compat.c @@ -665,7 +665,7 @@ of_at91_clk_pll_setup(struct device_node *np, if (!characteristics) return; =20 - hw =3D at91_clk_register_pll(regmap, name, parent_name, id, layout, + hw =3D at91_clk_register_pll(regmap, name, parent_name, NULL, id, layout, characteristics); if (IS_ERR(hw)) goto out_free_characteristics; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h index 87ab1211576f..0feaf8497b60 100644 --- a/drivers/clk/at91/pmc.h +++ b/drivers/clk/at91/pmc.h @@ -238,7 +238,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regm= ap, spinlock_t *lock, =20 struct clk_hw * __init at91_clk_register_pll(struct regmap *regmap, const char *name, - const char *parent_name, u8 id, + const char *parent_name, struct clk_parent_data *parent_data, u8 i= d, const struct clk_pll_layout *layout, const struct clk_pll_characteristics *characteristics); struct clk_hw * __init --=20 2.43.0