From nobody Sun Dec 14 17:58:56 2025 Received: from mail-244122.protonmail.ch (mail-244122.protonmail.ch [109.224.244.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB8BC3009C4 for ; Wed, 10 Dec 2025 17:30:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.122 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765387804; cv=none; b=XFuJDESSzCDGcXYcL/wWuhW8+gAPI1hN6sKkeCe9oA5smbdaDNx80gK1SqLblDbtd6HJL9zVofBRbP6Nc+aIS1nCyBGSr23AjCpNq82P/AkEoZfOa5xrCxU4lI/RaLGbkvj7h/1TJzcGlNO5JYUj968IZbJe2czMJj1NtVNnNVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765387804; c=relaxed/simple; bh=cLU1yDlyIufiMciF88eGTnMUwfesXy9yINZ4eeqk2+I=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LPP3J16sxL101HBOzFhPFXEfQSDJKqpXDLekgkpIRzxLmMrjH8LGuRRCZYqSaYHzMvomptcbpTG37l6eXNxPK0mr/DJN9L1vOegHAqkNgGU7PGooHNBTxyoTQdSvFX2Lqy3ey6KSWsGQToC3GXr0BEmsze1Fl4TtlVJk3TBdp2M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=DZ+OMy1x; arc=none smtp.client-ip=109.224.244.122 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="DZ+OMy1x" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1765387794; x=1765646994; bh=tF6uZeqRtsc0uhEqsykdQtAU19tdI7CeSMEK1HyPxRA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=DZ+OMy1xQ3Whr/Tamd7lFwNLJou8hMTMNIY+HODuob8gvgrRAwkIBSpqMQdC9NvnK dgnvPQS+lzl87gfV3WDyjT+EFYETzRPM03Q13Tg+lW++lNIFll497eIVVyatea7AHZ IDe1CyypCVGFBXjjaxpOxUeBepysK2a7GEUiTcJ7ul2tdAud4OHPHR1O7CwAK6LHUJ I4v2Ow8E8sYI2+mGjZplbnJLjVWgVz8lQUGTVJqhas2YVoKRd7Ms+7rV/2F8UuytZy cBI/maO5ikt0rnLKg+wBKZd9hZ5AaD6VyNA1utsiZslBlDMVmBPi+Y53uPvhukrfBA 3a0G3b72hg2ug== Date: Wed, 10 Dec 2025 17:29:52 +0000 To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra From: Maciej Wieczor-Retman Cc: m.wieczorretman@pm.me, Maciej Wieczor-Retman , Alexander Potapenko , linux-kernel@vger.kernel.org Subject: [PATCH v7 10/15] x86/mm: LAM initialization Message-ID: <45dec73dcc8eefeaf00f0d0ab7dd65c6d1cd13d8.1765386422.git.m.wieczorretman@pm.me> In-Reply-To: References: Feedback-ID: 164464600:user:proton X-Pm-Message-ID: db9a7589834f5597b92a772b6e06b450fdeda4cc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maciej Wieczor-Retman To make use of KASAN's tag based mode on x86, Linear Address Masking (LAM) needs to be enabled. To do that the 28th bit in CR4 has to be set. Set the bit in early memory initialization. When launching secondary CPUs the LAM bit gets lost. To avoid this add it in a mask in head_64.S. The bitmask permits some bits of CR4 to pass from the primary CPU to the secondary CPUs without being cleared. Signed-off-by: Maciej Wieczor-Retman Acked-by: Alexander Potapenko --- Changelog v7: - Add Alexander's acked-by tag. Changelog v6: - boot_cpu_has() -> cpu_feature_enabled() arch/x86/kernel/head_64.S | 3 +++ arch/x86/mm/init.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 21816b48537c..c5a0bfbe280d 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -209,6 +209,9 @@ SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL) * there will be no global TLB entries after the execution." */ movl $(X86_CR4_PAE | X86_CR4_LA57), %edx +#ifdef CONFIG_ADDRESS_MASKING + orl $X86_CR4_LAM_SUP, %edx +#endif #ifdef CONFIG_X86_MCE /* * Preserve CR4.MCE if the kernel will enable #MC support. diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c index 8bf6ad4b9400..a8442b255481 100644 --- a/arch/x86/mm/init.c +++ b/arch/x86/mm/init.c @@ -764,6 +764,9 @@ void __init init_mem_mapping(void) probe_page_size_mask(); setup_pcid(); =20 + if (cpu_feature_enabled(X86_FEATURE_LAM) && IS_ENABLED(CONFIG_KASAN_SW_TA= GS)) + cr4_set_bits_and_update_boot(X86_CR4_LAM_SUP); + #ifdef CONFIG_X86_64 end =3D max_pfn << PAGE_SHIFT; #else --=20 2.52.0