From nobody Fri Dec 19 20:16:10 2025 Received: from mx0a-00128a01.pphosted.com (mx0a-00128a01.pphosted.com [148.163.135.77]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3E7A1A270; Mon, 28 Apr 2025 00:14:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.135.77 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745799286; cv=none; b=ojhZZc1Uq4KJDYSVP9bQYVdUGQPMF/2haAf610S5K8a8GQSfgJaZa1LQ74b4wA1nQjQJrzy9gHEPfpBi1NAhySvyP3WdLGTd98BeoJz0IqhOU1Q0VKpArKThNb8p+DZEGKXplX+Dl06cPJEKfeKJFxbfs5P7amYOUZUDF2YyQRk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745799286; c=relaxed/simple; bh=FbLCTy/TsJyeKFnDyOvNxfUT67BZ63uQUyzT4qlSiK4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=F1A1KAcpMvTBrtIi73kCJjov61dqCwATTK32ZcgUhgVz2cXm72Fgn50uEArTMFCGwFOq4SGm7Vf4N4+5U0MizXXoFbOJgzYyom+aVRhzpvNtN2j9u3gBI6twdihtPUrEfLi2ElSt1Mq96953H4zLCHNCabios9FFz59bFctFSYQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com; spf=pass smtp.mailfrom=analog.com; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b=LyFY7kHn; arc=none smtp.client-ip=148.163.135.77 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=analog.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=analog.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=analog.com header.i=@analog.com header.b="LyFY7kHn" Received: from pps.filterd (m0167089.ppops.net [127.0.0.1]) by mx0a-00128a01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53RMVEVZ019059; Sun, 27 Apr 2025 20:14:35 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=analog.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=DKIM; bh=j0VTB d6QBXYcq4AhGaLg8JMAyxL4fcu9dZOREe0rzl0=; b=LyFY7kHnnV8a88cuQzjXI w0s/hXcv9nrARbZ2PymiFiqcdFjWPkMbSWLFFbdgR4uOII6/0xp/LUnNx6ugAVYf RtpFuUUwupvkNJ5gGuQLkT2aJmtcXlGF9EMH3ZxhPUr3A/hm5X7nsualPD/kuVy2 LWL2aPyPvKnjPfjdVKnfcn+3ZrFhcr7gk1bS5d3M+zh5tXSbRYhXWcWIGywOtVEO JfacqEYvVRQBcyh5lvs80uOA0R4Z1OzpszYuQ8J8pGAaUkVf6EOPjNb4Q3TW/kLs qUSaYkJdofer9wa5UtnOWgzdnMzt5SqF41cm8qaD9lnNBlyFgeJiQGgsWjy92NcM Q== Received: from nwd2mta3.analog.com ([137.71.173.56]) by mx0a-00128a01.pphosted.com (PPS) with ESMTPS id 468vd6sbw7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 27 Apr 2025 20:14:35 -0400 (EDT) Received: from ASHBMBX8.ad.analog.com (ASHBMBX8.ad.analog.com [10.64.17.5]) by nwd2mta3.analog.com (8.14.7/8.14.7) with ESMTP id 53S0EYlc029065 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 27 Apr 2025 20:14:34 -0400 Received: from ASHBCASHYB5.ad.analog.com (10.64.17.133) by ASHBMBX8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Sun, 27 Apr 2025 20:14:34 -0400 Received: from ASHBMBX8.ad.analog.com (10.64.17.5) by ASHBCASHYB5.ad.analog.com (10.64.17.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.14; Sun, 27 Apr 2025 20:14:33 -0400 Received: from zeus.spd.analog.com (10.66.68.11) by ashbmbx8.ad.analog.com (10.64.17.5) with Microsoft SMTP Server id 15.2.986.14 via Frontend Transport; Sun, 27 Apr 2025 20:14:33 -0400 Received: from JSANTO12-L01.ad.analog.com ([10.65.60.206]) by zeus.spd.analog.com (8.15.1/8.15.1) with ESMTP id 53S0EI2p014653; Sun, 27 Apr 2025 20:14:21 -0400 From: Jonathan Santos To: , , , CC: Jonathan Santos , , , , , , , , , , , , , , , , "Pop Paul" Subject: [PATCH v6 10/11] iio: adc: ad7768-1: add filter type and oversampling ratio attributes Date: Sun, 27 Apr 2025 21:14:17 -0300 Message-ID: <4493dc2e3e0fb61ba3e8a0e54571998aaaaf46c8.1745605382.git.Jonathan.Santos@analog.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: NaWKEUnf7UqYyD9AFpbGM3-gQIZOTvPp X-Authority-Analysis: v=2.4 cv=b+Wy4sGx c=1 sm=1 tr=0 ts=680ec86b cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=XR8D0OoHHMoA:10 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=PqQXOG8vFxuAHkRQ7a0A:9 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNDI3MDIwMiBTYWx0ZWRfXxphXPBtbxfuc xuGp2l68w1eAXbo6e/KdS5BLdVKr3jIrD2Iro5SPgqjs0tvqzLyCbFYev0y0WmdXAKOSujZj6Vl OnFyZ6a5rNQ8wPEuYwoIk1XePYItd90jl6tlTsihhVxMEChbCVPwZt++tCmvAu//Cy4mtEdPyQ4 7NdV+HSseyyyubL6Oyg2YunAFSAZFj1kbhfJatUFY1vkljIhdnUU6r89C8fhyw2jvAhQlQI9xcx 8JoqyEntTpK6F8m3PHpoTkJFBW7LbNivCzt3+leZn9P5QYj0pf94rVW/Fu+Z9WLw4ZBFFI2yzMU xA7ds67IfXSDRAZU75BNJ9poh4+JkmOE6zin4WB4h/OD3rF5GSje5uMEVk911OfG9Jjf9xYqTTL nKvVaQApVYS+DDh6/grrVcjJaq8eRS8/0KzMITbrPvJdx4hqS6vklKvS3d6pV71J8j/qx0nF X-Proofpoint-ORIG-GUID: NaWKEUnf7UqYyD9AFpbGM3-gQIZOTvPp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-27_08,2025-04-24_02,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 priorityscore=1501 adultscore=0 mlxscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2504270202 Content-Type: text/plain; charset="utf-8" Separate filter type and decimation rate from the sampling frequency attribute. The new filter type attribute enables sinc3, sinc3+rej60 and wideband filters, which were previously unavailable. Previously, combining decimation and MCLK divider in the sampling frequency obscured performance trade-offs. Lower MCLK divider settings increase power usage, while lower decimation rates reduce precision by decreasing averaging. By creating an oversampling attribute, which controls the decimation, users gain finer control over performance. The addition of those attributes allows a wider range of sampling frequencies and more access to the device features. Sampling frequency table is updated after every digital filter parameter change. Reviewed-by: David Lechner Co-developed-by: Pop Paul Signed-off-by: Pop Paul Signed-off-by: Jonathan Santos --- v6 Changes: * Made sinc3 decimation rate calculation clearer as requested. * Renamed some filter functions to clarify the purpose. * Other nits. v5 Changes: * Addressed some nits. * Use the new new iio_device_claim/release_direct() functions. v4 Changes: * Sampling frequency table is dynamically updated after every filter configuration. v3 Changes: * removed unused variables. * included sinc3+rej60 filter type. * oversampling_ratio moved to info_mask_shared_by_type. * reordered functions to avoid forward declaration. * simplified regmap writes. * Removed locking. * replaced some helper functions for direct regmap_update_bits calls. * Addressed other nits. v2 Changes: * Decimation_rate attribute replaced for oversampling_ratio. --- drivers/iio/adc/ad7768-1.c | 363 ++++++++++++++++++++++++++++++------- 1 file changed, 293 insertions(+), 70 deletions(-) diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c index 10791a85d2c5..e2b8f12260a5 100644 --- a/drivers/iio/adc/ad7768-1.c +++ b/drivers/iio/adc/ad7768-1.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include =20 #include #include @@ -77,7 +79,7 @@ #define AD7768_PWR_PWRMODE(x) FIELD_PREP(AD7768_PWR_PWRMODE_MSK, x) =20 /* AD7768_REG_DIGITAL_FILTER */ -#define AD7768_DIG_FIL_FIL_MSK GENMASK(6, 4) +#define AD7768_DIG_FIL_FIL_MSK GENMASK(7, 4) #define AD7768_DIG_FIL_FIL(x) FIELD_PREP(AD7768_DIG_FIL_FIL_MSK, x) #define AD7768_DIG_FIL_DEC_MSK GENMASK(2, 0) #define AD7768_DIG_FIL_DEC_RATE(x) FIELD_PREP(AD7768_DIG_FIL_DEC_MSK, x) @@ -125,22 +127,20 @@ enum ad7768_mclk_div { AD7768_MCLK_DIV_2 }; =20 -enum ad7768_dec_rate { - AD7768_DEC_RATE_32 =3D 0, - AD7768_DEC_RATE_64 =3D 1, - AD7768_DEC_RATE_128 =3D 2, - AD7768_DEC_RATE_256 =3D 3, - AD7768_DEC_RATE_512 =3D 4, - AD7768_DEC_RATE_1024 =3D 5, - AD7768_DEC_RATE_8 =3D 9, - AD7768_DEC_RATE_16 =3D 10 +enum ad7768_filter_type { + AD7768_FILTER_SINC5, + AD7768_FILTER_SINC3, + AD7768_FILTER_WIDEBAND, + AD7768_FILTER_SINC3_REJ60, }; =20 -struct ad7768_clk_configuration { - enum ad7768_mclk_div mclk_div; - enum ad7768_dec_rate dec_rate; - unsigned int clk_div; - enum ad7768_pwrmode pwrmode; +enum ad7768_filter_regval { + AD7768_FILTER_REGVAL_SINC5 =3D 0, + AD7768_FILTER_REGVAL_SINC5_X8 =3D 1, + AD7768_FILTER_REGVAL_SINC5_X16 =3D 2, + AD7768_FILTER_REGVAL_SINC3 =3D 3, + AD7768_FILTER_REGVAL_WIDEBAND =3D 4, + AD7768_FILTER_REGVAL_SINC3_REJ60 =3D 11, }; =20 enum ad7768_scan_type { @@ -152,18 +152,39 @@ static const int ad7768_mclk_div_rates[4] =3D { 16, 8, 4, 2, }; =20 -static const struct ad7768_clk_configuration ad7768_clk_config[] =3D { - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_8, 16, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_16, 32, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_32, 64, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_64, 128, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_2, AD7768_DEC_RATE_128, 256, AD7768_FAST_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_128, 512, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_256, 1024, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_512, 2048, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_4, AD7768_DEC_RATE_1024, 4096, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_8, AD7768_DEC_RATE_1024, 8192, AD7768_MED_MODE }, - { AD7768_MCLK_DIV_16, AD7768_DEC_RATE_1024, 16384, AD7768_ECO_MODE }, +static const int ad7768_dec_rate_values[8] =3D { + 8, 16, 32, 64, 128, 256, 512, 1024, +}; + +/* Decimation Rate range for each filter type */ +static const int ad7768_dec_rate_range[][3] =3D { + [AD7768_FILTER_SINC5] =3D { 8, 8, 1024 }, + [AD7768_FILTER_SINC3] =3D { 32, 32, 163840 }, + [AD7768_FILTER_WIDEBAND] =3D { 32, 32, 1024 }, + [AD7768_FILTER_SINC3_REJ60] =3D { 32, 32, 163840 }, +}; + +/* + * The AD7768-1 supports three primary filter types: + * Sinc5, Sinc3, and Wideband. + * However, the filter register values can also encode additional paramete= rs + * such as decimation rates and 60Hz rejection. This utility array separat= es + * the filter type from these parameters. + */ +static const int ad7768_filter_regval_to_type[] =3D { + [AD7768_FILTER_REGVAL_SINC5] =3D AD7768_FILTER_SINC5, + [AD7768_FILTER_REGVAL_SINC5_X8] =3D AD7768_FILTER_SINC5, + [AD7768_FILTER_REGVAL_SINC5_X16] =3D AD7768_FILTER_SINC5, + [AD7768_FILTER_REGVAL_SINC3] =3D AD7768_FILTER_SINC3, + [AD7768_FILTER_REGVAL_WIDEBAND] =3D AD7768_FILTER_WIDEBAND, + [AD7768_FILTER_REGVAL_SINC3_REJ60] =3D AD7768_FILTER_SINC3_REJ60, +}; + +static const char * const ad7768_filter_enum[] =3D { + [AD7768_FILTER_SINC5] =3D "sinc5", + [AD7768_FILTER_SINC3] =3D "sinc3", + [AD7768_FILTER_WIDEBAND] =3D "wideband", + [AD7768_FILTER_SINC3_REJ60] =3D "sinc3+rej60" }; =20 static const struct iio_scan_type ad7768_scan_type[] =3D { @@ -182,13 +203,34 @@ static const struct iio_scan_type ad7768_scan_type[] = =3D { }, }; =20 +static int ad7768_get_filter_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan); +static int ad7768_set_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan, unsigned int filter); + +static const struct iio_enum ad7768_filter_type_iio_enum =3D { + .items =3D ad7768_filter_enum, + .num_items =3D ARRAY_SIZE(ad7768_filter_enum), + .set =3D ad7768_set_fil_type_attr, + .get =3D ad7768_get_filter_type_attr, +}; + +static struct iio_chan_spec_ext_info ad7768_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_iio_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ad7768_filter_type_= iio_enum), + { } +}; + static const struct iio_chan_spec ad7768_channels[] =3D { { .type =3D IIO_VOLTAGE, .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), + .info_mask_shared_by_type_available =3D BIT(IIO_CHAN_INFO_OVERSAMPLING_R= ATIO), .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), .info_mask_shared_by_all_available =3D BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info =3D ad7768_ext_info, .indexed =3D 1, .channel =3D 0, .scan_index =3D 0, @@ -208,9 +250,12 @@ struct ad7768_state { struct clk *mclk; struct gpio_chip gpiochip; unsigned int mclk_freq; - unsigned int dec_rate; + unsigned int mclk_div; + unsigned int oversampling_ratio; + enum ad7768_filter_type filter_type; unsigned int samp_freq; - unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_clk_config)]; + unsigned int samp_freq_avail[ARRAY_SIZE(ad7768_mclk_div_rates)]; + unsigned int samp_freq_avail_len; struct completion completion; struct iio_trigger *trig; struct gpio_desc *gpio_sync_in; @@ -317,11 +362,35 @@ static int ad7768_send_sync_pulse(struct ad7768_state= *st) =20 static void ad7768_fill_samp_freq_tbl(struct ad7768_state *st) { - int i; + int i, freq_filtered, len =3D 0; + + freq_filtered =3D DIV_ROUND_CLOSEST(st->mclk_freq, st->oversampling_ratio= ); + for (i =3D 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { + st->samp_freq_avail[len] =3D DIV_ROUND_CLOSEST(freq_filtered, + ad7768_mclk_div_rates[i]); + /* Sampling frequency cannot be lower than the minimum of 50 SPS */ + if (st->samp_freq_avail[len] >=3D 50) + len++; + } + st->samp_freq_avail_len =3D len; +} + +static int ad7768_set_mclk_div(struct ad7768_state *st, unsigned int mclk_= div) +{ + unsigned int mclk_div_value; =20 - for (i =3D 0; i < ARRAY_SIZE(ad7768_clk_config); i++) - st->samp_freq_avail[i] =3D DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[i].clk_div); + mclk_div_value =3D AD7768_PWR_MCLK_DIV(mclk_div); + /* + * Set power mode based on mclk_div value. + * ECO_MODE is only recommended for MCLK_DIV 16 + */ + mclk_div_value |=3D mclk_div > AD7768_MCLK_DIV_16 ? + AD7768_PWR_PWRMODE(AD7768_FAST_MODE) : + AD7768_PWR_PWRMODE(AD7768_ECO_MODE); + + return regmap_update_bits(st->regmap, AD7768_REG_POWER_CLOCK, + AD7768_PWR_MCLK_DIV_MSK | AD7768_PWR_PWRMODE_MSK, + mclk_div_value); } =20 static int ad7768_set_mode(struct ad7768_state *st, @@ -357,7 +426,7 @@ static int ad7768_scan_direct(struct iio_dev *indio_dev) * register provides 24-bit data, the precision is reduced by * right-shifting the read value by 8 bits. */ - if (st->dec_rate =3D=3D 8) + if (st->oversampling_ratio =3D=3D 8) readval >>=3D 8; =20 /* @@ -404,22 +473,110 @@ static int ad7768_reg_access(struct iio_dev *indio_d= ev, return ret; } =20 -static int ad7768_set_dig_fil(struct ad7768_state *st, - enum ad7768_dec_rate dec_rate) +static int ad7768_set_sinc3_dec_rate(struct ad7768_state *st, + unsigned int dec_rate) { - unsigned int mode; + unsigned int max_dec_rate; + u8 dec_rate_reg[2]; + u16 regval; int ret; =20 - if (dec_rate =3D=3D AD7768_DEC_RATE_8 || dec_rate =3D=3D AD7768_DEC_RATE_= 16) - mode =3D AD7768_DIG_FIL_FIL(dec_rate); - else - mode =3D AD7768_DIG_FIL_DEC_RATE(dec_rate); + /* + * Maximum dec_rate is limited by the MCLK_DIV value + * and by the ODR. The edge case is for MCLK_DIV =3D 2 + * ODR =3D 50 SPS. + * max_dec_rate <=3D MCLK / (2 * 50) + */ + max_dec_rate =3D st->mclk_freq / 100; + dec_rate =3D clamp_t(unsigned int, dec_rate, 32, max_dec_rate); + /* + * Calculate the equivalent value to sinc3 decimation ratio + * to be written on the SINC3_DEC_RATE register: + * Value =3D (DEC_RATE / 32) -1 + */ + dec_rate =3D DIV_ROUND_UP(dec_rate, 32) - 1; =20 - ret =3D regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, mode); - if (ret < 0) + /* + * The SINC3_DEC_RATE value is a 13-bit value split across two + * registers: MSB [12:8] and LSB [7:0]. Prepare the 13-bit value using + * FIELD_PREP and store it with the right endianness in dec_rate_reg. + */ + regval =3D FIELD_PREP(GENMASK(12, 0), dec_rate); + put_unaligned_be16(regval, dec_rate_reg); + ret =3D regmap_bulk_write(st->regmap, AD7768_REG_SINC3_DEC_RATE_MSB, + dec_rate_reg, 2); + if (ret) + return ret; + + st->oversampling_ratio =3D (dec_rate + 1) * 32; + + return 0; +} + +static int ad7768_configure_dig_fil(struct iio_dev *dev, + enum ad7768_filter_type filter_type, + unsigned int dec_rate) +{ + struct ad7768_state *st =3D iio_priv(dev); + unsigned int dec_rate_idx, dig_filter_regval; + int ret; + + switch (filter_type) { + case AD7768_FILTER_SINC3: + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3); + break; + case AD7768_FILTER_SINC3_REJ60: + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC3_REJ6= 0); + break; + case AD7768_FILTER_WIDEBAND: + /* Skip decimations 8 and 16, not supported by the wideband filter */ + dec_rate_idx =3D find_closest(dec_rate, &ad7768_dec_rate_values[2], + ARRAY_SIZE(ad7768_dec_rate_values) - 2); + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_WIDEBAND) | + AD7768_DIG_FIL_DEC_RATE(dec_rate_idx); + /* Correct the index offset */ + dec_rate_idx +=3D 2; + break; + case AD7768_FILTER_SINC5: + dec_rate_idx =3D find_closest(dec_rate, ad7768_dec_rate_values, + ARRAY_SIZE(ad7768_dec_rate_values)); + + /* + * Decimations 8 (idx 0) and 16 (idx 1) are set in the + * FILTER[6:4] field. The other decimations are set in the + * DEC_RATE[2:0] field, and the idx need to be offsetted by two. + */ + if (dec_rate_idx =3D=3D 0) + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X8); + else if (dec_rate_idx =3D=3D 1) + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5_X16= ); + else + dig_filter_regval =3D AD7768_DIG_FIL_FIL(AD7768_FILTER_REGVAL_SINC5) | + AD7768_DIG_FIL_DEC_RATE(dec_rate_idx - 2); + break; + } + + ret =3D regmap_write(st->regmap, AD7768_REG_DIGITAL_FILTER, dig_filter_re= gval); + if (ret) return ret; =20 - /* A sync-in pulse is required every time the filter dec rate changes */ + st->filter_type =3D filter_type; + /* + * The decimation for SINC3 filters are configured in different + * registers + */ + if (filter_type =3D=3D AD7768_FILTER_SINC3 || + filter_type =3D=3D AD7768_FILTER_SINC3_REJ60) { + ret =3D ad7768_set_sinc3_dec_rate(st, dec_rate); + if (ret) + return ret; + } else { + st->oversampling_ratio =3D ad7768_dec_rate_values[dec_rate_idx]; + } + + ad7768_fill_samp_freq_tbl(st); + + /* A sync-in pulse is required after every configuration change */ return ad7768_send_sync_pulse(st); } =20 @@ -542,43 +699,69 @@ static int ad7768_gpio_init(struct iio_dev *indio_dev) static int ad7768_set_freq(struct ad7768_state *st, unsigned int freq) { - unsigned int diff_new, diff_old, pwr_mode, i, idx; + unsigned int diff_new, diff_old, i, idx; int res, ret; =20 + freq =3D clamp_t(unsigned int, freq, 50, 1024000); diff_old =3D U32_MAX; idx =3D 0; =20 - res =3D DIV_ROUND_CLOSEST(st->mclk_freq, freq); + if (freq =3D=3D 0) + return -EINVAL; + + res =3D DIV_ROUND_CLOSEST(st->mclk_freq, freq * st->oversampling_ratio); =20 /* Find the closest match for the desired sampling frequency */ - for (i =3D 0; i < ARRAY_SIZE(ad7768_clk_config); i++) { - diff_new =3D abs(res - ad7768_clk_config[i].clk_div); + for (i =3D 0; i < ARRAY_SIZE(ad7768_mclk_div_rates); i++) { + diff_new =3D abs(res - ad7768_mclk_div_rates[i]); if (diff_new < diff_old) { diff_old =3D diff_new; idx =3D i; } } =20 - /* - * Set both the mclk_div and pwrmode with a single write to the - * POWER_CLOCK register - */ - pwr_mode =3D AD7768_PWR_MCLK_DIV(ad7768_clk_config[idx].mclk_div) | - AD7768_PWR_PWRMODE(ad7768_clk_config[idx].pwrmode); - ret =3D regmap_write(st->regmap, AD7768_REG_POWER_CLOCK, pwr_mode); - if (ret < 0) + /* Set both the mclk_div and pwrmode */ + ret =3D ad7768_set_mclk_div(st, idx); + if (ret) return ret; =20 - ret =3D ad7768_set_dig_fil(st, ad7768_clk_config[idx].dec_rate); - if (ret < 0) + st->samp_freq =3D DIV_ROUND_CLOSEST(st->mclk_freq, + ad7768_mclk_div_rates[idx] * st->oversampling_ratio); + + /* A sync-in pulse is required after every configuration change */ + return ad7768_send_sync_pulse(st); +} + +static int ad7768_set_fil_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan, + unsigned int filter) +{ + struct ad7768_state *st =3D iio_priv(dev); + int ret; + + ret =3D ad7768_configure_dig_fil(dev, filter, st->oversampling_ratio); + if (ret) return ret; =20 - st->dec_rate =3D ad7768_clk_config[idx].clk_div / - ad7768_mclk_div_rates[ad7768_clk_config[idx].mclk_div]; - st->samp_freq =3D DIV_ROUND_CLOSEST(st->mclk_freq, - ad7768_clk_config[idx].clk_div); + /* Update sampling frequency */ + return ad7768_set_freq(st, st->samp_freq); +} =20 - return 0; +static int ad7768_get_filter_type_attr(struct iio_dev *dev, + const struct iio_chan_spec *chan) +{ + struct ad7768_state *st =3D iio_priv(dev); + int ret; + unsigned int mode; + + ret =3D regmap_read(st->regmap, AD7768_REG_DIGITAL_FILTER, &mode); + if (ret) + return ret; + + mode =3D FIELD_GET(AD7768_DIG_FIL_FIL_MSK, mode); + + /* From the register value, get the corresponding filter type */ + return ad7768_filter_regval_to_type[mode]; } =20 static int ad7768_read_raw(struct iio_dev *indio_dev, @@ -620,6 +803,11 @@ static int ad7768_read_raw(struct iio_dev *indio_dev, case IIO_CHAN_INFO_SAMP_FREQ: *val =3D st->samp_freq; =20 + return IIO_VAL_INT; + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *val =3D st->oversampling_ratio; + return IIO_VAL_INT; } =20 @@ -634,9 +822,13 @@ static int ad7768_read_avail(struct iio_dev *indio_dev, struct ad7768_state *st =3D iio_priv(indio_dev); =20 switch (info) { + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + *vals =3D (int *)ad7768_dec_rate_range[st->filter_type]; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; case IIO_CHAN_INFO_SAMP_FREQ: *vals =3D (int *)st->samp_freq_avail; - *length =3D ARRAY_SIZE(ad7768_clk_config); + *length =3D st->samp_freq_avail_len; *type =3D IIO_VAL_INT; return IIO_AVAIL_LIST; default: @@ -644,20 +836,44 @@ static int ad7768_read_avail(struct iio_dev *indio_de= v, } } =20 -static int ad7768_write_raw(struct iio_dev *indio_dev, - struct iio_chan_spec const *chan, - int val, int val2, long info) +static int __ad7768_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) { struct ad7768_state *st =3D iio_priv(indio_dev); + int ret; =20 switch (info) { case IIO_CHAN_INFO_SAMP_FREQ: return ad7768_set_freq(st, val); + + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + ret =3D ad7768_configure_dig_fil(indio_dev, st->filter_type, val); + if (ret) + return ret; + + /* Update sampling frequency */ + return ad7768_set_freq(st, st->samp_freq); default: return -EINVAL; } } =20 +static int ad7768_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, int val2, long info) +{ + int ret; + + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + + ret =3D __ad7768_write_raw(indio_dev, chan, val, val2, info); + iio_device_release_direct(indio_dev); + + return ret; +} + static int ad7768_read_label(struct iio_dev *indio_dev, const struct iio_chan_spec *chan, char *label) { @@ -671,7 +887,7 @@ static int ad7768_get_current_scan_type(const struct ii= o_dev *indio_dev, { struct ad7768_state *st =3D iio_priv(indio_dev); =20 - return st->dec_rate =3D=3D 8 ? AD7768_SCAN_TYPE_HIGH_SPEED : + return st->oversampling_ratio =3D=3D 8 ? AD7768_SCAN_TYPE_HIGH_SPEED : AD7768_SCAN_TYPE_NORMAL; } =20 @@ -825,6 +1041,14 @@ static int ad7768_setup(struct iio_dev *indio_dev) return ret; } =20 + /* + * Set Default Digital Filter configuration: + * SINC5 filter with x32 Decimation rate + */ + ret =3D ad7768_configure_dig_fil(indio_dev, AD7768_FILTER_SINC5, 32); + if (ret) + return ret; + /* Set the default sampling frequency to 32000 kSPS */ return ad7768_set_freq(st, 32000); } @@ -1172,7 +1396,6 @@ static int ad7768_probe(struct spi_device *spi) return PTR_ERR(st->mclk); =20 st->mclk_freq =3D clk_get_rate(st->mclk); - ad7768_fill_samp_freq_tbl(st); =20 indio_dev->channels =3D ad7768_channels; indio_dev->num_channels =3D ARRAY_SIZE(ad7768_channels); --=20 2.34.1