From nobody Thu Oct 2 09:18:59 2025 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5401D2C08AA; Thu, 18 Sep 2025 21:16:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.153.233 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758230191; cv=none; b=nKtRB30nC6OseEg4Q2Py/5OYQiPMpwhtwGO1Uxiy0xWX+OMDWLfZK/00SrQDrWFQgLVb9RyW1LyGL601Mbsu3fwAR5nMQyjygoftNVeDKJ0T8Eccxga0igzoi+Z6E5S7ZcJiAJs+mtKRNQAHALcxRotpsZxXHPv/nBrAScIE5Qg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758230191; c=relaxed/simple; bh=EGNab37xwDaXeQqQ4XsAZk+vGgUUKqm2uIGGIuG5b8M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=O7H6CzOFZ4rM9bh+FlpsUSirsFOysk7hTtPFvg0l3GyRQxrwI+gmgkvkSSzi29UCRtPwKFf83cW66os+dIARUUE6iMb5ugoKYQx3hQKPt83MdamTggVmzlu5OO57I4UTI2dGfWcVvqT3eyxjlh3w6eXx7lLeht1hrSOA6uV8LgI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=Gxi29Njc; arc=none smtp.client-ip=68.232.153.233 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="Gxi29Njc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1758230190; x=1789766190; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EGNab37xwDaXeQqQ4XsAZk+vGgUUKqm2uIGGIuG5b8M=; b=Gxi29Njc8sWhJ2ES8Kfwb0CFG1cNsNX00RXM4PX03DC2eiBLBQfYueWs LDZMB+aKcL24DFX+b2zqc4KXc7xQ7iJpL9l25qhwqUywnTOclG/uQIsue Y3Cemzd/xXgCUiICEQIZbO6y24WOfwErVRXsakw8zJt6uMx84TVimaFnL +MhhlDvTbhGNFDaOX0ZefPLavCT9PecGpi8h4H30ql/rjtuETAmJGeSgp jKjUdCGHO092tjlMZQzYKZz8wOc+xdFJMzOK4Zm8tD1bCIhPljZfA3vrO x1KIGL6bLnFoq7V2XyAOf5PPwzxXS0YmydQhFlhFhgL9R9Kcvc8pE0zN+ w==; X-CSE-ConnectionGUID: 31sRM3ybQuOqhqj3gb2ViA== X-CSE-MsgGUID: vV/vjRtuTMyIB2N+XpB5cA== X-IronPort-AV: E=Sophos;i="6.18,276,1751266800"; d="scan'208";a="278071377" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 18 Sep 2025 14:16:22 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.58; Thu, 18 Sep 2025 14:15:51 -0700 Received: from ryan-Precision-3630-Tower.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Thu, 18 Sep 2025 14:15:51 -0700 From: To: , , , , CC: , , , , "Ryan Wanner" Subject: [PATCH v4 03/31] clk: at91: sam9x75: switch to parent_hw and parent_data Date: Thu, 18 Sep 2025 14:15:45 -0700 Message-ID: <42d01c533eecf4018174ab5c3e0a6130e3dc34f0.1758226719.git.Ryan.Wanner@microchip.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ryan Wanner Switch SAM9X75 clocks to use parent_hw and parent_data. Having parent_hw instead of parent names improves to clock registration speed and re-parenting. The USBCLK will be updated in subsequent patches that update the clock registration functions to use parent_hw and parent_data. __clk_get_hw() will be removed in subsequent patches in this series. Signed-off-by: Ryan Wanner --- drivers/clk/at91/sam9x7.c | 308 +++++++++++++++++++++----------------- 1 file changed, 173 insertions(+), 135 deletions(-) diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c index 89868a0aeaba..cb5849da494f 100644 --- a/drivers/clk/at91/sam9x7.c +++ b/drivers/clk/at91/sam9x7.c @@ -33,10 +33,22 @@ enum pll_ids { PLL_ID_UPLL, PLL_ID_AUDIO, PLL_ID_LVDS, - PLL_ID_PLLA_DIV2, PLL_ID_MAX, }; =20 +/* + * PLL component identifier + * @PLL_COMPID_FRAC: Fractional PLL component identifier + * @PLL_COMPID_DIV0: 1st PLL divider component identifier + * @PLL_COMPID_DIV1: 2nd PLL divider component identifier + */ +enum pll_component_id { + PLL_COMPID_FRAC, + PLL_COMPID_DIV0, + PLL_COMPID_DIV1, + PLL_COMPID_MAX, +}; + /** * enum pll_type - PLL type identifiers * @PLL_TYPE_FRAC: fractional PLL identifier @@ -185,6 +197,18 @@ static const struct clk_pll_layout pll_divio_layout = =3D { .endiv_shift =3D 30, }; =20 +/* + * SAM9X7 PLL possible parents + * @SAM9X7_PLL_PARENT_MAINCK: MAINCK is PLL a parent + * @SAM9X7_PLL_PARENT_MAIN_XTAL: MAIN XTAL is a PLL parent + * @SAM9X7_PLL_PARENT_FRACCK: Frac PLL is a PLL parent (for PLL dividers) + */ +enum sam9x7_pll_parent { + SAM9X7_PLL_PARENT_MAINCK, + SAM9X7_PLL_PARENT_MAIN_XTAL, + SAM9X7_PLL_PARENT_FRACCK +}; + /* * PLL clocks description * @n: clock name @@ -192,22 +216,24 @@ static const struct clk_pll_layout pll_divio_layout = =3D { * @l: clock layout * @t: clock type * @c: pll characteristics + * @hw: pointer to clk_hw * @f: clock flags * @eid: export index in sam9x7->chws[] array */ -static const struct { +static struct { const char *n; - const char *p; const struct clk_pll_layout *l; u8 t; const struct clk_pll_characteristics *c; + struct clk_hw *hw; unsigned long f; + enum sam9x7_pll_parent p; u8 eid; -} sam9x7_plls[][3] =3D { +} sam9x7_plls[][PLL_COMPID_MAX] =3D { [PLL_ID_PLLA] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "plla_fracck", - .p =3D "mainck", + .p =3D SAM9X7_PLL_PARENT_MAINCK, .l =3D &plla_frac_layout, .t =3D PLL_TYPE_FRAC, /* @@ -218,9 +244,9 @@ static const struct { .c =3D &plla_characteristics, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "plla_divpmcck", - .p =3D "plla_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .t =3D PLL_TYPE_DIV, /* This feeds CPU. It should not be disabled */ @@ -228,21 +254,35 @@ static const struct { .eid =3D PMC_PLLACK, .c =3D &plla_characteristics, }, + + [PLL_COMPID_DIV1] =3D { + .n =3D "plla_div2pmcck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, + .l =3D &plladiv2_divpmc_layout, + /* + * This may feed critical parts of the system like timers. + * It should not be disabled. + */ + .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, + .c =3D &plladiv2_characteristics, + .eid =3D PMC_PLLADIV2, + .t =3D PLL_TYPE_DIV, + }, }, =20 [PLL_ID_UPLL] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "upll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .t =3D PLL_TYPE_FRAC, .f =3D CLK_SET_RATE_GATE, .c =3D &upll_characteristics, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "upll_divpmcck", - .p =3D "upll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .t =3D PLL_TYPE_DIV, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | @@ -253,18 +293,18 @@ static const struct { }, =20 [PLL_ID_AUDIO] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "audiopll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .f =3D CLK_SET_RATE_GATE, .c =3D &audiopll_characteristics, .t =3D PLL_TYPE_FRAC, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "audiopll_divpmcck", - .p =3D "audiopll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -273,9 +313,9 @@ static const struct { .t =3D PLL_TYPE_DIV, }, =20 - { + [PLL_COMPID_DIV1] =3D { .n =3D "audiopll_diviock", - .p =3D "audiopll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divio_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -286,18 +326,18 @@ static const struct { }, =20 [PLL_ID_LVDS] =3D { - { + [PLL_COMPID_FRAC] =3D { .n =3D "lvdspll_fracck", - .p =3D "main_osc", + .p =3D SAM9X7_PLL_PARENT_MAIN_XTAL, .l =3D &pll_frac_layout, .f =3D CLK_SET_RATE_GATE, .c =3D &lvdspll_characteristics, .t =3D PLL_TYPE_FRAC, }, =20 - { + [PLL_COMPID_DIV0] =3D { .n =3D "lvdspll_divpmcck", - .p =3D "lvdspll_fracck", + .p =3D SAM9X7_PLL_PARENT_FRACCK, .l =3D &pll_divpmc_layout, .f =3D CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_RATE_PARENT, @@ -306,22 +346,6 @@ static const struct { .t =3D PLL_TYPE_DIV, }, }, - - [PLL_ID_PLLA_DIV2] =3D { - { - .n =3D "plla_div2pmcck", - .p =3D "plla_fracck", - .l =3D &plladiv2_divpmc_layout, - /* - * This may feed critical parts of the system like timers. - * It should not be disabled. - */ - .f =3D CLK_IS_CRITICAL | CLK_SET_RATE_GATE, - .c =3D &plladiv2_characteristics, - .eid =3D PMC_PLLADIV2, - .t =3D PLL_TYPE_DIV, - }, - }, }; =20 static const struct clk_programmable_layout sam9x7_programmable_layout =3D= { @@ -339,9 +363,9 @@ static const struct clk_pcr_layout sam9x7_pcr_layout = =3D { .pid_mask =3D GENMASK(6, 0), }; =20 -static const struct { +static struct { char *n; - char *p; + struct clk_hw *parent_hw; u8 id; unsigned long flags; } sam9x7_systemck[] =3D { @@ -349,10 +373,10 @@ static const struct { * ddrck feeds DDR controller and is enabled by bootloader thus we need * to keep it enabled in case there is no Linux consumer for it. */ - { .n =3D "ddrck", .p =3D "masterck_div", .id =3D 2, .flags =3D CLK_IS_CR= ITICAL }, - { .n =3D "uhpck", .p =3D "usbck", .id =3D 6 }, - { .n =3D "pck0", .p =3D "prog0", .id =3D 8 }, - { .n =3D "pck1", .p =3D "prog1", .id =3D 9 }, + { .n =3D "ddrck", .id =3D 2, .flags =3D CLK_IS_CRITICAL }, + { .n =3D "uhpck", .id =3D 6 }, + { .n =3D "pck0", .id =3D 8 }, + { .n =3D "pck1", .id =3D 9 }, }; =20 /* @@ -426,7 +450,8 @@ static const struct { /* * Generic clock description * @n: clock name - * @pp: PLL parents + * @pp: PLL parents (entry formed by PLL components identifiers + * (see enum pll_component_id)) * @pp_mux_table: PLL parents mux table * @r: clock output range * @pp_chg_id: id in parent array of changeable PLL parent @@ -435,7 +460,10 @@ static const struct { */ static const struct { const char *n; - const char *pp[8]; + struct { + int pll_id; + int pll_compid; + } pp[8]; const char pp_mux_table[8]; struct clk_range r; int pp_chg_id; @@ -445,7 +473,7 @@ static const struct { { .n =3D "flex0_gclk", .id =3D 5, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -454,7 +482,7 @@ static const struct { { .n =3D "flex1_gclk", .id =3D 6, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -463,7 +491,7 @@ static const struct { { .n =3D "flex2_gclk", .id =3D 7, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -472,7 +500,7 @@ static const struct { { .n =3D "flex3_gclk", .id =3D 8, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -481,7 +509,7 @@ static const struct { { .n =3D "flex6_gclk", .id =3D 9, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -490,7 +518,7 @@ static const struct { { .n =3D "flex7_gclk", .id =3D 10, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -499,7 +527,7 @@ static const struct { { .n =3D "flex8_gclk", .id =3D 11, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -509,7 +537,7 @@ static const struct { .n =3D "sdmmc0_gclk", .id =3D 12, .r =3D { .max =3D 105000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -518,7 +546,7 @@ static const struct { { .n =3D "flex4_gclk", .id =3D 13, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -527,7 +555,7 @@ static const struct { { .n =3D "flex5_gclk", .id =3D 14, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -536,7 +564,7 @@ static const struct { { .n =3D "flex9_gclk", .id =3D 15, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -545,7 +573,7 @@ static const struct { { .n =3D "flex10_gclk", .id =3D 16, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -554,7 +582,7 @@ static const struct { { .n =3D "tcb0_gclk", .id =3D 17, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -563,7 +591,7 @@ static const struct { { .n =3D "adc_gclk", .id =3D 19, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -573,7 +601,7 @@ static const struct { .n =3D "lcd_gclk", .id =3D 25, .r =3D { .max =3D 75000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -583,7 +611,7 @@ static const struct { .n =3D "sdmmc1_gclk", .id =3D 26, .r =3D { .max =3D 105000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -593,7 +621,7 @@ static const struct { .n =3D "mcan0_gclk", .id =3D 29, .r =3D { .max =3D 80000000 }, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -603,7 +631,7 @@ static const struct { .n =3D "mcan1_gclk", .id =3D 30, .r =3D { .max =3D 80000000 }, - .pp =3D { "upll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(UPLL, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, D= IV1), }, .pp_mux_table =3D { 5, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -612,7 +640,7 @@ static const struct { { .n =3D "flex11_gclk", .id =3D 32, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -621,7 +649,7 @@ static const struct { { .n =3D "flex12_gclk", .id =3D 33, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -631,7 +659,7 @@ static const struct { .n =3D "i2s_gclk", .id =3D 34, .r =3D { .max =3D 100000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -641,7 +669,7 @@ static const struct { .n =3D "qspi_gclk", .id =3D 35, .r =3D { .max =3D 200000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -650,7 +678,7 @@ static const struct { { .n =3D "pit64b0_gclk", .id =3D 37, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -660,7 +688,7 @@ static const struct { .n =3D "classd_gclk", .id =3D 42, .r =3D { .max =3D 100000000 }, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -669,7 +697,7 @@ static const struct { { .n =3D "tcb1_gclk", .id =3D 45, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -678,7 +706,7 @@ static const struct { { .n =3D "dbgu_gclk", .id =3D 47, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -688,7 +716,7 @@ static const struct { .n =3D "mipiphy_gclk", .id =3D 55, .r =3D { .max =3D 27000000 }, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -697,7 +725,7 @@ static const struct { { .n =3D "pit64b1_gclk", .id =3D 58, - .pp =3D { "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(PLLA, DIV1), }, .pp_mux_table =3D { 8, }, .pp_count =3D 1, .pp_chg_id =3D INT_MIN, @@ -706,7 +734,7 @@ static const struct { { .n =3D "gmac_gclk", .id =3D 67, - .pp =3D { "audiopll_divpmcck", "plla_div2pmcck", }, + .pp =3D { PLL_IDS_TO_ARR_ENTRY(AUDIO, DIV0), PLL_IDS_TO_ARR_ENTRY(PLLA, = DIV1), }, .pp_mux_table =3D { 6, 8, }, .pp_count =3D 2, .pp_chg_id =3D INT_MIN, @@ -716,33 +744,25 @@ static const struct { static void __init sam9x7_pmc_setup(struct device_node *np) { struct clk_range range =3D CLK_RANGE(0, 0); - const char *td_slck_name, *md_slck_name, *mainxtal_name; + const char *main_xtal_name; struct pmc_data *sam9x7_pmc; const char *parent_names[9]; void **clk_mux_buffer =3D NULL; int clk_mux_buffer_size =3D 0; - struct clk_hw *main_osc_hw; struct regmap *regmap; - struct clk_hw *hw; + struct clk_hw *hw, *main_rc_hw, *main_osc_hw, *main_xtal_hw; + struct clk_hw *td_slck_hw, *md_slck_hw, *usbck_hw; + struct clk_hw *parent_hws[9]; int i, j; =20 - i =3D of_property_match_string(np, "clock-names", "td_slck"); - if (i < 0) - return; - - td_slck_name =3D of_clk_get_parent_name(np, i); - - i =3D of_property_match_string(np, "clock-names", "md_slck"); - if (i < 0) - return; - - md_slck_name =3D of_clk_get_parent_name(np, i); - + td_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "td_slck")); + md_slck_hw =3D __clk_get_hw(of_clk_get_by_name(np, "md_slck")); i =3D of_property_match_string(np, "clock-names", "main_xtal"); - if (i < 0) + + if (!td_slck_hw || !md_slck_hw || !i) return; - mainxtal_name =3D of_clk_get_parent_name(np, i); =20 + main_xtal_name =3D of_clk_get_parent_name(np, i); regmap =3D device_node_to_regmap(np); if (IS_ERR(regmap)) return; @@ -760,26 +780,25 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) if (!clk_mux_buffer) goto err_free; =20 - hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, - 50000000); - if (IS_ERR(hw)) + main_rc_hw =3D at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000= 000, + 50000000); + if (IS_ERR(main_rc_hw)) goto err_free; =20 - hw =3D at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL= , 0); - if (IS_ERR(hw)) + main_osc_hw =3D at91_clk_register_main_osc(regmap, "main_osc", NULL, &AT9= 1_CLK_PD_NAME(main_xtal_name), 0); + if (IS_ERR(main_osc_hw)) goto err_free; - main_osc_hw =3D hw; =20 - parent_names[0] =3D "main_rc_osc"; - parent_names[1] =3D "main_osc"; - hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL= , 2); + parent_hws[0] =3D main_rc_hw; + parent_hws[1] =3D main_osc_hw; + hw =3D at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_hws, = 2); if (IS_ERR(hw)) goto err_free; =20 sam9x7_pmc->chws[PMC_MAIN] =3D hw; =20 for (i =3D 0; i < PLL_ID_MAX; i++) { - for (j =3D 0; j < 3; j++) { + for (j =3D 0; j < PLL_COMPID_MAX; j++) { struct clk_hw *parent_hw; =20 if (!sam9x7_plls[i][j].n) @@ -787,19 +806,23 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) =20 switch (sam9x7_plls[i][j].t) { case PLL_TYPE_FRAC: - if (!strcmp(sam9x7_plls[i][j].p, "mainck")) + switch (sam9x7_plls[i][j].p) { + case SAM9X7_PLL_PARENT_MAINCK: parent_hw =3D sam9x7_pmc->chws[PMC_MAIN]; - else if (!strcmp(sam9x7_plls[i][j].p, "main_osc")) - parent_hw =3D main_osc_hw; - else - parent_hw =3D __clk_get_hw(of_clk_get_by_name - (np, sam9x7_plls[i][j].p)); + break; + case SAM9X7_PLL_PARENT_MAIN_XTAL: + parent_hw =3D main_xtal_hw; + break; + default: + /* Should not happen. */ + parent_hw =3D NULL; + break; + } =20 hw =3D sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - sam9x7_plls[i][j].p, - parent_hw, i, + NULL, parent_hw, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f); @@ -809,7 +832,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) hw =3D sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, sam9x7_plls[i][j].n, - sam9x7_plls[i][j].p, NULL, i, + NULL, sam9x7_plls[i][0].hw, i, sam9x7_plls[i][j].c, sam9x7_plls[i][j].l, sam9x7_plls[i][j].f, 0); @@ -822,23 +845,24 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) if (IS_ERR(hw)) goto err_free; =20 + sam9x7_plls[i][j].hw =3D hw; if (sam9x7_plls[i][j].eid) sam9x7_pmc->chws[sam9x7_plls[i][j].eid] =3D hw; } } =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D "mainck"; - parent_names[2] =3D "plla_divpmcck"; - parent_names[3] =3D "upll_divpmcck"; + parent_hws[0] =3D md_slck_hw; + parent_hws[1] =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_hws[2] =3D sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV0].hw; + parent_hws[3] =3D sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV0].hw; hw =3D at91_clk_register_master_pres(regmap, "masterck_pres", 4, - parent_names, NULL, &sam9x7_master_layout, + NULL, parent_hws, &sam9x7_master_layout, &mck_characteristics, &mck_lock); if (IS_ERR(hw)) goto err_free; =20 hw =3D at91_clk_register_master_div(regmap, "masterck_div", - "masterck_pres", NULL, &sam9x7_master_layout, + NULL, hw, &sam9x7_master_layout, &mck_characteristics, &mck_lock, CLK_SET_RATE_GATE, 0); if (IS_ERR(hw)) @@ -849,24 +873,24 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) parent_names[0] =3D "plla_divpmcck"; parent_names[1] =3D "upll_divpmcck"; parent_names[2] =3D "main_osc"; - hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); - if (IS_ERR(hw)) + usbck_hw =3D sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3); + if (IS_ERR(usbck_hw)) goto err_free; =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D td_slck_name; - parent_names[2] =3D "mainck"; - parent_names[3] =3D "masterck_div"; - parent_names[4] =3D "plla_divpmcck"; - parent_names[5] =3D "upll_divpmcck"; - parent_names[6] =3D "audiopll_divpmcck"; + parent_hws[0] =3D md_slck_hw; + parent_hws[1] =3D td_slck_hw; + parent_hws[2] =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_hws[3] =3D sam9x7_pmc->chws[PMC_MCK]; + parent_hws[4] =3D sam9x7_plls[PLL_ID_PLLA][PLL_COMPID_DIV0].hw; + parent_hws[5] =3D sam9x7_plls[PLL_ID_UPLL][PLL_COMPID_DIV0].hw; + parent_hws[6] =3D sam9x7_plls[PLL_ID_AUDIO][PLL_COMPID_DIV0].hw; for (i =3D 0; i < 2; i++) { char name[6]; =20 snprintf(name, sizeof(name), "prog%d", i); =20 hw =3D at91_clk_register_programmable(regmap, name, - parent_names, NULL, 7, i, + NULL, parent_hws, 7, i, &sam9x7_programmable_layout, NULL); if (IS_ERR(hw)) @@ -875,9 +899,14 @@ static void __init sam9x7_pmc_setup(struct device_node= *np) sam9x7_pmc->pchws[i] =3D hw; } =20 + /* Set systemck parent hws. */ + sam9x7_systemck[0].parent_hw =3D sam9x7_pmc->chws[PMC_MCK]; + sam9x7_systemck[1].parent_hw =3D usbck_hw; + sam9x7_systemck[2].parent_hw =3D sam9x7_pmc->pchws[0]; + sam9x7_systemck[3].parent_hw =3D sam9x7_pmc->pchws[1]; for (i =3D 0; i < ARRAY_SIZE(sam9x7_systemck); i++) { hw =3D at91_clk_register_system(regmap, sam9x7_systemck[i].n, - sam9x7_systemck[i].p, NULL, + NULL, sam9x7_systemck[i].parent_hw, sam9x7_systemck[i].id, sam9x7_systemck[i].flags); if (IS_ERR(hw)) @@ -890,7 +919,7 @@ static void __init sam9x7_pmc_setup(struct device_node = *np) hw =3D at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_periphck[i].n, - "masterck_div", NULL, + NULL, sam9x7_pmc->chws[PMC_MCK], sam9x7_periphck[i].id, &range, INT_MIN, sam9x7_periphck[i].f); @@ -900,12 +929,13 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) sam9x7_pmc->phws[sam9x7_periphck[i].id] =3D hw; } =20 - parent_names[0] =3D md_slck_name; - parent_names[1] =3D td_slck_name; - parent_names[2] =3D "mainck"; - parent_names[3] =3D "masterck_div"; + parent_hws[0] =3D md_slck_hw; + parent_hws[1] =3D td_slck_hw; + parent_hws[2] =3D sam9x7_pmc->chws[PMC_MAIN]; + parent_hws[3] =3D sam9x7_pmc->chws[PMC_MCK]; for (i =3D 0; i < ARRAY_SIZE(sam9x7_gck); i++) { u8 num_parents =3D 4 + sam9x7_gck[i].pp_count; + struct clk_hw *tmp_parent_hws[6]; u32 *mux_table; =20 mux_table =3D kmalloc_array(num_parents, sizeof(*mux_table), @@ -916,13 +946,21 @@ static void __init sam9x7_pmc_setup(struct device_nod= e *np) PMC_INIT_TABLE(mux_table, 4); PMC_FILL_TABLE(&mux_table[4], sam9x7_gck[i].pp_mux_table, sam9x7_gck[i].pp_count); - PMC_FILL_TABLE(&parent_names[4], sam9x7_gck[i].pp, + + for (j =3D 0; j < sam9x7_gck[i].pp_count; j++) { + u8 pll_id =3D sam9x7_gck[i].pp[j].pll_id; + u8 pll_compid =3D sam9x7_gck[i].pp[j].pll_compid; + + tmp_parent_hws[j] =3D sam9x7_plls[pll_id][pll_compid].hw; + } + + PMC_FILL_TABLE(&parent_hws[4], tmp_parent_hws, sam9x7_gck[i].pp_count); =20 hw =3D at91_clk_register_generated(regmap, &pmc_pcr_lock, &sam9x7_pcr_layout, sam9x7_gck[i].n, - parent_names, NULL, mux_table, + NULL, parent_hws, mux_table, num_parents, sam9x7_gck[i].id, &sam9x7_gck[i].r, --=20 2.43.0