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smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=t-chip.com.cn; spf=pass smtp.mailfrom=t-chip.com.cn; arc=none smtp.client-ip=114.132.67.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=t-chip.com.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=t-chip.com.cn X-QQ-mid: esmtpsz16t1757381636tc3bd904e X-QQ-Originating-IP: p0b1CcCoNWAvqnYHZqcy4fPY6UpyXVvkrqVg7S7Jqzg= Received: from localhost.localdomain ( [183.51.121.90]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 09 Sep 2025 09:33:49 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 13416220292544305717 EX-QQ-RecipientCnt: 16 From: Kaison Deng To: Rob Herring , Jimmy Hon , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Wayne Chou , Quentin Schulz , Dragan Simic , Jonas Karlman , FUKAUMI Naoki , Peter Robinson , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kaison Deng Subject: [PATCH v2 2/2] arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT Date: Tue, 9 Sep 2025 09:31:48 +0800 Message-Id: <42ae6d16ed9162582e7b03cbad661a7950c0db55.1757322046.git.dkx@t-chip.com.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: esmtpsz:t-chip.com.cn:qybglogicsvrsz:qybglogicsvrsz4a-0 X-QQ-XMAILINFO: NtZ5dn2+LGG54LbklJsdErSwGl8OApyHXfmmI/R0Fo/pzldQ7Bwm8guz 6eXg1hTvQI1qHF7K/P+cGgXpsoSm4qo/lOQCke/yheujn+xuLeB2I19fp+ip/niTKos6llo OdhqkmcD6mvSiUjD0R9jBPcei5q1az1lYBOCnEM26xeqsYGDxoHvjKd2dYyCTR2/i69G3Hp sBaUgQmsdo2sqRTgUTdtWQ2+mgLXBdDPYNr2PzqW628Mher2UgoVbey5JyN9Dn77ou96Jfb U8S8zZadogRSj+63AP9j0ohsTke81kvMKq9lXn+C6D+2xBabJ6ekOesw4WqMadpF/G00rEx CU0t3KtgKvT1KWGp8FBcvrIP09/Km2+qyoIHe+HQN+kgDAQPXr4Vja85lHDAKkMJZCxEUUM FKY+l1yDnUUZJotrZp2T5sJZTGJZADFXoMvrIcHHVkvSvhWjQ2Zzf6VdNAxhEODbXLYkeXD X4HZTmb3iCN1+/sdU0RrQUzu5UyJ1aJPsD2MKRVP3L6HBzYtMwEauIoP8gYgIM3hg4ejdhF /6VTO8a1srkgQPeh8BzF6e1xik+sCXNcip3xx8QduRR3l7sdLirfXn+31XET7kEjwu/HSN6 BHO6LKE9HCOoxFZbAWSsuPsFjNeK/n/Qfa89LRWPHNM/bdWiCO+AI4MAQYjW9qeH8VCS9rx 67lF4USFVnsC5pcJz94m+ud8ddixVBFvqRW/kqfEkfHRLUaMix8J3BqnUzqHY14tsz8kTrZ n4Np37lztED4qSIRqtQijvtrpuAraXi+mNUItsbTu2vlnuOzmA7TAhV/0K/vAKPd2Ikxw7G iG2A2FVIIBsADleZEYV7NQvEbu1Uy4vnTiw0N/NQuXezlXkKzp5FPbuMVz+71qJxi4ZPyMq eP9HnkB7Xpp9EcbrMx/u5mIVSN9duBh8kdATj8+S8gWrtbg9GiTr66reWJgVPpvrEdle7K3 jh+H0JtaRyuHHX+10Ckt1NoN1uLM4SIKPr3zovYj85wqKLYkMjVeBRN9YtLjwWUWAST3hz0 2vfn69VxKvJ1LW87Ksu+ul98z/fKf6S6uGHRa7P0Of1iCCOzaB7Q6VzKLlVkQ5cbZai1iRz csQUEmhytCYZcBuKa0apBMTFcvkXDclPiZ0HxvpsymPTIOF3/yrsefdUFgKR+PKoA== X-QQ-XMRINFO: MPJ6Tf5t3I/ycC2BItcBVIA= X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" Link: https://en.t-firefly.com/product/industry/rocrk3588rt The Firefly ROC-RK3588-RT is RK3588 based SBC featuring: - TF card slot - SATA 2242 socket - 1x USB 3.0 Port, 1x USB 2.0 Port, 1x Typec Port - 1x HDMI 2.1 out, 1x HDMI 2.0 out - 2x Gigabit Ethernet, 1x 2.5G Ethernet - M.2 E-KEY for Extended WiFI and Bluetoolh - ES8388 on-board sound codec - jack in/out - RTC - LED: WORK, DIY Signed-off-by: Kaison Deng --- Changes in v2: - Update the description to match the device tree - Adjust the descriptions of the model and compatible properties - Add audio support for hdmi0 and hdmi1 - Adjust the properties of sdhci in alphabetical order --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../arm64/boot/dts/rockchip/rk3588-roc-rt.dts | 1136 +++++++++++++++++ 2 files changed, 1137 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 9d56d4146b20..ad684e3831bc 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -181,6 +181,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-orangepi-5-max.= dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-orangepi-5-ultra.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-quartzpro64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-roc-rt.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5-itx.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-pcie-ep.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts b/arch/arm64/bo= ot/dts/rockchip/rk3588-roc-rt.dts new file mode 100644 index 000000000000..f2c254615c3a --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-roc-rt.dts @@ -0,0 +1,1136 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Firefly Technology Co. Ltd + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "Firefly ROC-RK3588-RT"; + compatible =3D "firefly,roc-rk3588-rt", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdhci; + mmc1 =3D &sdmmc; + ethernet0 =3D &gmac0; + ethernet1 =3D &gmac1; + }; + + adc-keys-0 { + compatible =3D "adc-keys"; + io-channels =3D <&saradc 1>; + io-channel-names =3D "buttons"; + keyup-threshold-microvolt =3D <1800000>; + poll-interval =3D <100>; + + button-recovery { + label =3D "Recovery"; + linux,code =3D ; + press-threshold-microvolt =3D <17000>; + }; + }; + + analog-sound { + compatible =3D "simple-audio-card"; + pinctrl-0 =3D <&hp_detect>; + pinctrl-names =3D "default"; + simple-audio-card,aux-devs =3D <&_headphones>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,hp-det-gpios =3D <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + simple-audio-card,mclk-fs =3D <384>; + simple-audio-card,name =3D "rockchip-es8388"; + simple-audio-card,pin-switches =3D "Headphones"; + simple-audio-card,routing =3D + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphones Amplifier INL", "LOUT1", + "Headphones Amplifier INR", "ROUT1", + "Headphones", "Headphones Amplifier OUTL", + "Headphones", "Headphones Amplifier OUTR", + "LINPUT1", "Microphone Jack", + "RINPUT1", "Microphone Jack", + "LINPUT2", "Onboard Microphone", + "RINPUT2", "Onboard Microphone"; + simple-audio-card,widgets =3D + "Microphone", "Microphone Jack", + "Microphone", "Onboard Microphone", + "Headphone", "Headphones", + "Speaker", "Speaker"; + + simple-audio-card,cpu { + sound-dai =3D <&i2s0_8ch>; + }; + + simple-audio-card,codec { + sound-dai =3D <&es8388>; + system-clock-frequency =3D <12288000>; + }; + }; + + amp_headphones: headphones-amplifier { + compatible =3D "simple-audio-amplifier"; + enable-gpios =3D <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&headphone_amplifier_en>; + sound-name-prefix =3D "Headphones Amplifier"; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + fan: pwm-fan { + compatible =3D "pwm-fan"; + cooling-levels =3D <0 70 75 80 100>; + fan-supply =3D <&vcc5v0_sys>; + #cooling-cells =3D <2>; + pwms =3D <&pwm15 0 50000 1>; + }; + + hdmi0-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint =3D <&hdmi0_out_con>; + }; + }; + }; + + hdmi1-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint =3D <&hdmi1_out_con>; + }; + }; + }; + + leds { + compatible =3D "gpio-leds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&led_pins>; + + power_led { + gpios =3D <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "default-on"; + }; + + user_led { + gpios =3D <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "disk-activity"; + }; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&typec5v_pwren>; + regulator-name =3D "vbus5v0_typec"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-name =3D "vcc12v_dcin"; + }; + + vcc3v3_sata2: vcc3v3-sata2 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3_sata2"; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc3v3_sd_s0: regulator-vcc3v3-sd-s0 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3_sd_s0"; + vin-supply =3D <&vcc_3v3_s3>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc3v3_wlan: regulator-vcc3v3-wlan { + compatible =3D "regulator-fixed"; + enable-active-high; + gpios =3D <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_pwren>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "wlan-en"; + vin-supply =3D <&vcc3v3_sys>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vcc5v0_host"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host_en>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc5v0_host3: regulator-vcc5v0-host3 { + compatible =3D "regulator-fixed"; + enable-active-high; + gpio =3D <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "vcc5v0_host3"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc5v0_host3_en>; + vin-supply =3D <&vcc5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vcc_1v1_nldo_s3"; + vin-supply =3D <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&combphy1_ps { + status =3D "okay"; +}; + +&combphy2_psu { + status =3D "okay"; +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy0>; + phy-mode =3D "rgmii-rxid"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + tx_delay =3D <0x47>; + status =3D "okay"; +}; + +&gmac1 { + clock_in_out =3D "output"; + phy-handle =3D <&rgmii_phy1>; + phy-mode =3D "rgmii-rxid"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + tx_delay =3D <0x42>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + sram-supply =3D <&vdd_gpu_mem_s0>; + status =3D "okay"; +}; + +&hdmi0 { + status =3D "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint =3D <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint =3D <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status =3D "okay"; +}; + +&hdmi1 { + status =3D "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint =3D <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint =3D <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status =3D "okay"; +}; + +&hdptxphy0 { + status =3D "okay"; +}; + +&hdptxphy1 { + status =3D "okay"; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0m2_xfer>; + status =3D "okay"; + + /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */ + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + reg =3D <0x43>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3m0_xfer>; + + es8388: audio-codec@11 { + compatible =3D "everest,es8388", "everest,es8328"; + reg =3D <0x11>; + clocks =3D <&cru I2S0_8CH_MCLKOUT>; + AVDD-supply =3D <&vcc_1v8_s0>; + DVDD-supply =3D <&vcc_1v8_s0>; + HPVDD-supply =3D <&vcc_3v3_s0>; + PVDD-supply =3D <&vcc_1v8_s0>; + assigned-clocks =3D <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + }; +}; + +&i2c6 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6m0_xfer>; + + usbc0: usb-typec@22 { + compatible =3D "fcs,fusb302"; + reg =3D <0x22>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usbc0_int>; + vbus-supply =3D <&vbus5v0_typec>; + status =3D "okay"; + + usb_con: connector { + compatible =3D "usb-c-connector"; + label =3D "USB-C"; + data-role =3D "dual"; + op-sink-microwatt =3D <1000000>; + power-role =3D "dual"; + sink-pdos =3D + ; + source-pdos =3D + ; + try-power-role =3D "source"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint =3D <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg =3D <1>; + + usbc0_role_sw: endpoint { + remote-endpoint =3D <&dwc3_0_role_switch>; + }; + }; + + port@2 { + reg =3D <2>; + + dp_altmode_mux: endpoint { + remote-endpoint =3D <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + wakeup-source; + }; +}; + +&i2s0_8ch { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2s0_lrck + &i2s0_mclk + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; + status =3D "okay"; +}; + +&i2s5_8ch { + status =3D "okay"; +}; + +&i2s6_8ch { + status =3D "okay"; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0x1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8211f_0_rst>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + }; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0x1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtl8211f_1_rst>; + reset-assert-us =3D <20000>; + reset-deassert-us =3D <100000>; + reset-gpios =3D <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; +}; + +&pcie2x1l0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_0_rst>, <&pcie2_0_wake>, <&pcie2_0_clkreq>; + reset-gpios =3D <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply =3D <&vcc3v3_wlan>; + status =3D "okay"; +}; + +&pcie2x1l2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2_2_rst>; + reset-gpios =3D <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status =3D "okay"; +}; + +&pd_gpu { + domain-supply =3D <&vdd_gpu_s0>; +}; + +&pinctrl { + audio { + hp_detect: headphone-detect { + rockchip,pins =3D <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + headphone_amplifier_en: headphone-amplifier-en { + rockchip,pins =3D <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio-leds { + led_pins: led-pins { + rockchip,pins =3D + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins =3D <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie2_0_wake: pcie2-0-wake { + rockchip,pins =3D <4 RK_PA4 4 &pcfg_pull_none>; + }; + + pcie2_0_clkreq: pcie2-0-clkreq { + rockchip,pins =3D <4 RK_PA3 4 &pcfg_pull_none>; + }; + + pcie2_2_rst: pcie2-2-rst { + rockchip,pins =3D <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_0_rst: rtl8211f-0-rst { + rockchip,pins =3D <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + rtl8211f_1_rst: rtl8211f-1-rst { + rockchip,pins =3D <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins =3D <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host3_en: vcc5v0-host3-en { + rockchip,pins =3D <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + typec5v_pwren: typec5v-pwren { + rockchip,pins =3D <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins =3D <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wlan { + wifi_pwren: wifi-pwren { + rockchip,pins =3D <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm15 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm15m2_pins>; +}; + +&saradc { + vref-supply =3D <&vcc_1v8_s0>; + status =3D "okay"; +}; + +&sdhci { + bus-width =3D <8>; + max-frequency =3D <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sdio; + no-sd; + non-removable; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-sd-highspeed; + disable-wp; + max-frequency =3D <150000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc3v3_sd_s0>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&spi2 { + assigned-clocks =3D <&cru CLK_SPI2>; + assigned-clock-rates =3D <200000000>; + num-cs =3D <1>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + status =3D "okay"; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0x0>; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency =3D <1000000>; + system-power-controller; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + avdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "avdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "avdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&sata2 { + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; + +&u2phy0 { + status =3D "okay"; +}; + +&u2phy0_otg { + status =3D "okay"; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&u2phy1_otg { + phy-supply =3D <&vcc5v0_host3>; + status =3D "okay"; +}; + +&u2phy2 { + status =3D "okay"; +}; + +&u2phy2_host { + phy-supply =3D <&vcc5v0_host>; + status =3D "okay"; +}; + +&u2phy3 { + status =3D "okay"; +}; + +&u2phy3_host { + phy-supply =3D <&vcc5v0_host3>; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; + +&usb_host0_ehci { + status =3D "okay"; +}; + +&usb_host0_ohci { + status =3D "okay"; +}; + +&usb_host0_xhci { + dr_mode =3D "otg"; + usb-role-switch; + status =3D "okay"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + dwc3_0_role_switch: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usbc0_role_sw>; + }; + }; +}; + +&usb_host1_ehci { + status =3D "okay"; +}; + +&usb_host1_ohci { + status =3D "okay"; +}; + +&usb_host1_xhci { + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usbdp_phy0 { + mode-switch; + orientation-switch; + sbu1-dc-gpios =3D <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios =3D <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + usbdp_phy0_orientation_switch: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux =3D <2 3>; + status =3D "okay"; +}; + +&vop { + status =3D "okay"; +}; + +&vop_mmu { + status =3D "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg =3D ; + remote-endpoint =3D <&hdmi0_in_vp0>; + }; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg =3D ; + remote-endpoint =3D <&hdmi1_in_vp1>; + }; +}; + --=20 2.25.1