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charset="utf-8" Content-ID: <3FA00DC9FDE12D4C946FCE55A5429D74@namprd10.prod.outlook.com> Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: gXpAMdoii8SiJMC9WxnbuUI4D9GoGev7SINuGP9GC1LP8B730QLbkBVxu2yAsXuSWSpetw3wxi6L6uCOly405P/HyEfp6/1bJixcwiMHvJGTJkPUXQUtAFNYvUZ0tTiODJ3fn9CU0qrGjyFLorw7QJ91n3COdT19MOPU7PTqqsiuy2QPLTwKRUq+j6zmywqZ9A/Is2uf5Aw/iSeYxh0d4GLEhlS4JVtHfDN4YlpNVXnXbobegKZvHfXrhQ9xHaWzHNuSch8JuHFNCPMIE7vL5thj/cUswvxFZqPAXS6uoVh2C4f8MNl+o3G2SY4BIF7JyNzftyGOgciKoO7379T3gJC57dhSUg/bpMu5L4MFJLGISmBOMENIrA0n1iHbIXul1in+MSkP2TkdgHpX/7QYcsFxw31yT71rM8vqWqgMWg4s1e9rwIVoe+dxLIXnZ6S01fDdfCPUZ2CLuiqxk6mY2/elO88PbopU23WvnEb9+ofXTVYgoFqPgxhHwp1VpDzmkQe5MVj9/rXAB11UPhQR05qAd3in6Qxw4ioZwO8b0eVBScufDlxDhJlScfaJNwrl6Rpy18zok20+fRr1q2d/9z1q+Z3ICV/xYjb1xjURrmg= X-OriginatorOrg: oracle.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CY8PR10MB6708.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5db46c9b-4d79-4060-48b9-08dcfe919114 X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Nov 2024 18:33:53.7263 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 4e2c6054-71cb-48f1-bd6c-3a9705aca71b X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: dnnkM1obDnVp/hpZ7/SLgELZ8B2gUYbkv6SrlkPOGEi32Wct6wEemiBTAaUS/fAQ6EyX99DdOejW458TFcHHHIZVMHBAY8IzNodLFT3nC78= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR10MB7279 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.62.30 definitions=2024-11-06_12,2024-11-06_01,2024-09-30_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 bulkscore=0 adultscore=0 mlxscore=0 malwarescore=0 suspectscore=0 phishscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2409260000 definitions=main-2411060143 X-Proofpoint-ORIG-GUID: T2mpwYck1LiJ5seRK3zkX797V-TxsJjn X-Proofpoint-GUID: T2mpwYck1LiJ5seRK3zkX797V-TxsJjn Hello, The following commit, which is part of 6.12 rc, does not work consistently = on systems with AMD processors vs. Intel: 70044df250d0: x86/pkeys: Update PKRU to enable all pkeys before XSAVE This zeroes out the pkeys in handle_signal() by calling sig_prepare_pkru(): /* * Enable all pkeys temporarily, so as to ensure that both the current * execution stack as well as the alternate signal stack are writeable. * The application can use any of the available pkeys to protect the * alternate signal stack, and we don't know which one it is, so enable * all. The PKRU register will be reset to init_pkru later in the flow, * in fpu__clear_user_states(), and it is the application's responsibility * to enable the appropriate pkey as the first step in the signal handler * so that the handler does not segfault. */ static inline u32 sig_prepare_pkru(void) { u32 orig_pkru =3D read_pkru(); write_pkru(0); return orig_pkru; } The write_pkru(0) call seems to set xinuse[9] to 0 on systems with AMD CPUs= (but not Intel), which means the user-defined PKRU value overwritten in th= e sigframe (in update_pkru_in_sigframe()) is not restored by XRSTOR and the= PKRU value stays at 0 when it returns back to userspace. Which is unexpect= ed. AMD: $ ./handler-pkru startup pkru =3D 0x55555554 changed in main thread pkru =3D 0xfffffff0 received signal 10 in signal handler pkru =3D 0x55555554 after usr1 signal pkru =3D 0x00000000 =E2=80=A6 xcr0 207 xcr0 AND xinuse 202 writing pkru 0 xcr0 207 xcr0 AND xinuse 2 Intel: $ ./handler-pkru startup pkru =3D 0x55555554 changed in main thread pkru =3D 0xfffffff0 received signal 10 in signal handler pkru =3D 0x55555554 after usr1 signal pkru =3D 0xfffffff0 =E2=80=A6 xcr0 2E7 xcr0 AND xinuse 2A2 writing pkru 0 xcr0 2E7 xcr0 AND xinuse 2A2 From the Intel manual: =E2=80=9C 13.6 PROCESSOR TRACKING OF XSAVE-MANAGED STATE The following notation describes the state of the init and modified optimiz= ations: =E2=80=A2 XINUSE denotes the state-component bitmap corresponding to the in= it optimization. If XINUSE[i] =3D 0, state component i is known to be in it= s initial configuration; otherwise XINUSE[i] =3D 1. It is possible for XINU= SE[i] to be 1 even when state component i is in its initial configuration. = On a processor that does not support the init optimization, XINUSE[i] is al= ways 1 for every value of i. ... =E2=80=A2 PKRU state. PKRU state is in its initial configuration if the val= ue of the PKRU is 0. ... 13.8.1 Standard Form of XRSTOR XRSTOR updates state component i based on the value of bit i in the XSTATE_= BV field of the XSAVE header: =E2=80=A2 If XSTATE_BV[i] =3D 0, the state component is set to its initial = configuration. Section 13.6 specifies the initial configuration of each sta= te component. The initial configuration of state component 1 pertains only to the XMM reg= isters and not to MXCSR. See below for the treatment of MXCSR =E2=80=A2 If XSTATE_BV[i] =3D 1, the state component is loaded with data fr= om the XSAVE area. See Section 13.5 for specifics for each state component = and for details regarding mode-specific operation and operation determined = by instruction prefixes. See Section 13.13 for details regarding faults cau= sed by memory accesses. =E2=80=9C The line =E2=80=9CPKRU state is in its initial configuration if the value o= f the PKRU is 0=E2=80=9D seems to imply that when the PKRU register is set = to 0, xinuse[9] is also automatically set to 0 and that is expected behavio= r, which causes XRSTOR to not load the register value from XSAVE area. But = we do not want xinuse[9] to be set to 0 here, as we want the PKRU value to = be correctly restored from the sigframe - otherwise it becomes a security i= ssue. I=E2=80=99m not really sure of the correct way to reset xinuse[9] to 1 (aft= er wrpkru(0)) - but something like this seems to work (thanks to Rudi Horn = for both finding the issue and suggesting this patch): diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index 1065ab995305..701a163f0ac5 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -68,9 +68,35 @@ static inline bool check_xstate_in_sigframe(struct fxreg= s_state __user *fxbuf, */ static inline int update_pkru_in_sigframe(struct xregs_state __user *buf, = u32 pkru) { + int err =3D 0; + if (unlikely(!cpu_feature_enabled(X86_FEATURE_OSPKE))) return 0; - return __put_user(pkru, (unsigned int __user *)get_xsave_addr_user(= buf, XFEATURE_PKRU)); + + if (pkru !=3D 0) { + err =3D __put_user(pkru, + (unsigned int __user *)get_xsave_addr_user( + buf, XFEATURE_PKRU)); + u64 xfeatures; + u64 __user *xfeaturesp =3D &buf->header.xfeatures; + + err |=3D __get_user(xfeatures, xfeaturesp); + + /* + * On some systems, when PKRU is set to 0, the corresponding + * XINUSE bit is also zeroed out, which causes XRSTOR to not + * load the register value from XSAVE area. Which means the + * PKRU value that was updated on the sigframe will be + * effectively discarded. + * + * Mark PKRU as in use so that it is restored correctly. + */ + if (!err & !(xfeatures & XFEATURE_MASK_PKRU)) { + xfeatures |=3D XFEATURE_MASK_PKRU; + err |=3D __put_user(xfeatures, xfeaturesp); + } + } } I=E2=80=99ve tested a version of this patch on both AMD and Intel systems a= nd it works. Please let me know if this is acceptable, or if there=E2=80=99s a better wa= y to do this. Thanks, Aruna