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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:47.1393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ac97e69b-0651-451f-bb22-08de595507de X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000143.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5798 Content-Type: text/plain; charset="utf-8" So far, an IOTLB tag (ASID or VMID) has been stored in the arm_smmu_domain structure. Its lifecycle is aligned with the smmu_domain. However, an IOTLB tag (ASID/VMID) will not be used: 1) Before being installed to CD/STE during a device attachment 2) After being removed from CD/STE during a device detachment Both (1) and (2) exactly align with the lifecycle of smmu_domain->invs. The bigger problem is that storing the IOTLB tag in struct arm_smmu_domain makes it difficult to share across SMMU instances, a common use case for a nesting parent domain. Store the IOTLB tags (old domain's and new domain's) in the state. This'll be forwarded to CD and STE entries, to replace the references of cd->asid and s2_cfg->vmid from the smmu_domain. Add a new arm_smmu_domain_get_iotlb_tag() helper provisionally copying the existing IOTLB tags from smmu_domain to fill arm_smmu_master_build_invs(). Later it will retrieve an IOTLB tag from the smmu_domain->invs or allocate a new one for the lifecycle issue. Suggested-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Jason Gunthorpe --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 6 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 78 ++++++++++++++------- 2 files changed, 60 insertions(+), 24 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 4f104c1baa67..73cb59c7d4b1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1111,11 +1111,13 @@ static inline bool arm_smmu_master_canwbs(struct ar= m_smmu_master *master) * @new_invs: for new domain, this is the new invs array to update domain-= >invs; * for old domain, this is the master->build_invs to pass in as= the * to_unref argument to an arm_smmu_invs_unref() call + * @tag: IOTLB cache tag (INV_TYPE_S1_ASID or INV_TYPE_S2_VMID) */ struct arm_smmu_inv_state { struct arm_smmu_invs __rcu **invs_ptr; struct arm_smmu_invs *old_invs; struct arm_smmu_invs *new_invs; + struct arm_smmu_inv tag; }; =20 struct arm_smmu_attach_state { @@ -1132,6 +1134,10 @@ struct arm_smmu_attach_state { bool ats_enabled; }; =20 +int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu, + struct arm_smmu_inv *tag); + int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, struct iommu_domain *new_domain); void arm_smmu_attach_commit(struct arm_smmu_attach_state *state); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9912262a0e3b..325eabb51c81 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3117,6 +3117,33 @@ static void arm_smmu_disable_iopf(struct arm_smmu_ma= ster *master, iopf_queue_remove_device(master->smmu->evtq.iopf, master->dev); } =20 +int arm_smmu_domain_get_iotlb_tag(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *smmu, + struct arm_smmu_inv *tag) +{ + /* Decide the type of the iotlb cache tag */ + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_SVA: + case ARM_SMMU_DOMAIN_S1: + tag->type =3D INV_TYPE_S1_ASID; + break; + case ARM_SMMU_DOMAIN_S2: + tag->type =3D INV_TYPE_S2_VMID; + break; + default: + return -EINVAL; + } + + tag->smmu =3D smmu; + + if (tag->type =3D=3D INV_TYPE_S1_ASID) + tag->id =3D smmu_domain->cd.asid; + else + tag->id =3D smmu_domain->s2_cfg.vmid; + + return 0; +} + static struct arm_smmu_inv * arm_smmu_master_build_inv(struct arm_smmu_master *master, enum arm_smmu_inv_type type, u32 id, ioasid_t ssid, @@ -3176,7 +3203,8 @@ arm_smmu_master_build_inv(struct arm_smmu_master *mas= ter, */ static struct arm_smmu_invs * arm_smmu_master_build_invs(struct arm_smmu_master *master, bool ats_enable= d, - ioasid_t ssid, struct arm_smmu_domain *smmu_domain) + ioasid_t ssid, struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag) { const bool nesting =3D smmu_domain->nest_parent; size_t pgsize =3D 0, i; @@ -3189,30 +3217,15 @@ arm_smmu_master_build_invs(struct arm_smmu_master *= master, bool ats_enabled, if (master->smmu->features & ARM_SMMU_FEAT_RANGE_INV) pgsize =3D __ffs(smmu_domain->domain.pgsize_bitmap); =20 - switch (smmu_domain->stage) { - case ARM_SMMU_DOMAIN_SVA: - case ARM_SMMU_DOMAIN_S1: - if (!arm_smmu_master_build_inv(master, INV_TYPE_S1_ASID, - smmu_domain->cd.asid, - IOMMU_NO_PASID, pgsize)) - return NULL; - break; - case ARM_SMMU_DOMAIN_S2: - if (!arm_smmu_master_build_inv(master, INV_TYPE_S2_VMID, - smmu_domain->s2_cfg.vmid, - IOMMU_NO_PASID, pgsize)) - return NULL; - break; - default: - WARN_ON(true); + if (!arm_smmu_master_build_inv(master, tag->type, tag->id, + IOMMU_NO_PASID, pgsize)) return NULL; - } =20 /* All the nested S1 ASIDs have to be flushed when S2 parent changes */ if (nesting) { - if (!arm_smmu_master_build_inv( - master, INV_TYPE_S2_VMID_S1_CLEAR, - smmu_domain->s2_cfg.vmid, IOMMU_NO_PASID, 0)) + if (!arm_smmu_master_build_inv(master, + INV_TYPE_S2_VMID_S1_CLEAR, + tag->id, IOMMU_NO_PASID, 0)) return NULL; } =20 @@ -3280,7 +3293,9 @@ static int arm_smmu_attach_prepare_invs(struct arm_sm= mu_attach_state *state, struct arm_smmu_domain *old_smmu_domain =3D to_smmu_domain_devices(state->old_domain); struct arm_smmu_master *master =3D state->master; + struct arm_smmu_device *smmu =3D master->smmu; ioasid_t ssid =3D state->ssid; + int ret; =20 /* * At this point a NULL domain indicates the domain doesn't use the @@ -3294,8 +3309,16 @@ static int arm_smmu_attach_prepare_invs(struct arm_s= mmu_attach_state *state, invst->old_invs =3D rcu_dereference_protected( new_smmu_domain->invs, lockdep_is_held(&arm_smmu_asid_lock)); - build_invs =3D arm_smmu_master_build_invs( - master, state->ats_enabled, ssid, new_smmu_domain); + + ret =3D arm_smmu_domain_get_iotlb_tag(new_smmu_domain, smmu, + &invst->tag); + if (ret) + return ret; + + build_invs =3D arm_smmu_master_build_invs(master, + state->ats_enabled, + ssid, new_smmu_domain, + &invst->tag); if (!build_invs) return -EINVAL; =20 @@ -3316,9 +3339,16 @@ static int arm_smmu_attach_prepare_invs(struct arm_s= mmu_attach_state *state, invst->old_invs =3D rcu_dereference_protected( old_smmu_domain->invs, lockdep_is_held(&arm_smmu_asid_lock)); + + ret =3D arm_smmu_domain_get_iotlb_tag(old_smmu_domain, smmu, + &invst->tag); + if (WARN_ON(ret)) + return ret; + /* For old_smmu_domain, new_invs points to master->build_invs */ invst->new_invs =3D arm_smmu_master_build_invs( - master, master->ats_enabled, ssid, old_smmu_domain); + master, master->ats_enabled, ssid, old_smmu_domain, + &invst->tag); } =20 return 0; --=20 2.43.0