From nobody Tue Feb 10 09:30:46 2026 Received: from gollum.nazgul.ch (gollum.nazgul.ch [81.221.21.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5A4213BACC; Sat, 17 Aug 2024 07:08:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.221.21.253 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878497; cv=none; b=ABD0SoNbHslAVTPFPYTem1VHV5UWFza4skeifc8ULZIFL0wtN/Wzlx9bL9r/zXEg7sVdhLstPMep2ADuKe/Wg/sOU9P9ZNGQpM3G9F199M6l8wOV2rS9er8V87gzOwxSN0rZlrxCs3iVeZJhtYlcckvsWc2Oa6uuapQGq3yfZvk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878497; c=relaxed/simple; bh=yzE+jy8b8afb5issZkSmbEdmvFnKwx2rjcFKUOjTdLY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GOCX5djk/ftFvPOSKTULOvXWhQDNrWRF3jCdklaTnllITwCVToA+5u8bKFUCkMYEx2o7r9w0uxPrEYQtLViKTsgWtjv0eqwYs8uExAarK95OthnA33Ent8z/FTvEHqJf9DLrbTmfq3/j5hlZ+cdTXkIeSmyTCGDi1pawBJfYAnM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch; spf=pass smtp.mailfrom=nazgul.ch; arc=none smtp.client-ip=81.221.21.253 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nazgul.ch Received: from localhost (gollum.nazgul.ch [local]) by gollum.nazgul.ch (OpenSMTPD) with ESMTPA id 4bb5a486; Sat, 17 Aug 2024 09:08:12 +0200 (CEST) Date: Sat, 17 Aug 2024 09:08:12 +0200 From: Marcus Glocker To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Konrad Dybcio Subject: [PATCH v4 1/6] dt-bindings: crypto: Add X1E80100 Crypto Engine Message-ID: <6xex326bp6rwybul4tfviiry37oz6qerkzov2czfiig56khnfn@o6nuxcudj3cn> References: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the inline crypto engine compatible for the Qualcomm X1E80100. Signed-off-by: Marcus Glocker --- .../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-en= gine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-eng= ine.yaml index 0304f074cf08..915db3d28892 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.ya= ml @@ -19,6 +19,7 @@ properties: - qcom,sm8450-inline-crypto-engine - qcom,sm8550-inline-crypto-engine - qcom,sm8650-inline-crypto-engine + - qcom,x1e80100-inline-crypto-engine - const: qcom,inline-crypto-engine =20 reg: --=20 2.39.2 From nobody Tue Feb 10 09:30:46 2026 Received: from gollum.nazgul.ch (gollum.nazgul.ch [81.221.21.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE9F620E6; Sat, 17 Aug 2024 07:09:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.221.21.253 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878592; cv=none; b=IhDBd4GOCztvVZMfwakB+GMjsQ1iB3nSkrIylhRJz8wLIUYmrq61F3nmgZmz39K5Ay+qqumFq+ibY8+KBsqjR7+GlVbMTccWHcyd6NfUoDYiS51Yy9guP6Vt383fayGh6oCqyZPjryRiw3gooiRZPdDUTgptZKNJwViYPP9T2SM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878592; c=relaxed/simple; bh=JvzCCKC0wSDVJ7SbM4PZ7/+vtSnSPsAjuaz/BWOT4dc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=HP1aiJcXm9y4p7Oitjq7TwsiFaqw7FbL0u6IUXxBbU1vq39Cc/HVkZC5QeanfMsuyoNv5Wf3kHQMPBCYe5XAYeotou0NWdNh3klYYHrJ1P3gXw2gMbM98FthAXCmqLSTANsRbVizxV9FFSwbGQRd9U/WnezWZmhLvZNTy7xvz8Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch; spf=pass smtp.mailfrom=nazgul.ch; arc=none smtp.client-ip=81.221.21.253 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nazgul.ch Received: from localhost (gollum.nazgul.ch [local]) by gollum.nazgul.ch (OpenSMTPD) with ESMTPA id f5ee78ed; Sat, 17 Aug 2024 09:09:47 +0200 (CEST) Date: Sat, 17 Aug 2024 09:09:47 +0200 From: Marcus Glocker To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Konrad Dybcio Subject: [PATCH v4 2/6] dt-bindings: phy: Add X1E80100 UFS Message-ID: References: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the qmp ufs phy compatible for the Qualcomm X1E80100. Signed-off-by: Marcus Glocker --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-ph= y.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.ya= ml index f9cfbd0b2de6..c8a61cddb311 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -35,6 +35,7 @@ properties: - qcom,sm8475-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy + - qcom,x1e80100-qmp-ufs-phy =20 reg: maxItems: 1 @@ -102,6 +103,7 @@ allOf: - qcom,sm8475-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy + - qcom,x1e80100-qmp-ufs-phy then: properties: clocks: --=20 2.39.2 From nobody Tue Feb 10 09:30:46 2026 Received: from gollum.nazgul.ch (gollum.nazgul.ch [81.221.21.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C8C4820E6; Sat, 17 Aug 2024 07:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.221.21.253 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878666; cv=none; b=dGgGWEF0FCE6gKa3Mv0SBdNyjEL+RWOqFM+iownMDz+hKLQZ6tG3+daxU9J0dH3Z1AG8dSY6h194+4jMkVTB8OM/Tc16tnkbdG9/fPrIH1qwAxxTYEBsejOiwkUDU5ZEM5/04mEGuARKPu33UZPy0io/gPjJRaceV0S80Jmrv04= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878666; c=relaxed/simple; bh=RmPTMHik1Ww+as8nGPYipMDCD9r8HigdtJBXkQE/E1E=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=BuztWNKuahE6uRUwAt2tjBvT9arlGEW8YFmFzvVjAdDvaXk+dg/qBEpfxtYBVZAZCsvHunWVKGwWB9JrYwis9/ymshyl2CwaIepm9npNLBETWFLtt2eTh8LMK55Mouoxtf+95hFaVj9kmsUeAiBN5PQb4vJGw4SaKL99Z842cVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch; spf=pass smtp.mailfrom=nazgul.ch; arc=none smtp.client-ip=81.221.21.253 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nazgul.ch Received: from localhost (gollum.nazgul.ch [local]) by gollum.nazgul.ch (OpenSMTPD) with ESMTPA id 6fd25548; Sat, 17 Aug 2024 09:11:01 +0200 (CEST) Date: Sat, 17 Aug 2024 09:11:01 +0200 From: Marcus Glocker To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Konrad Dybcio Subject: [PATCH v4 3/6] dt-bindings: ufs: Add X1E80100 UFS Message-ID: References: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the ufs host controller compatible for the Qualcomm X1E80100. Signed-off-by: Marcus Glocker --- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Document= ation/devicetree/bindings/ufs/qcom,ufs.yaml index 25a5edeea164..4cb3fea53651 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml @@ -41,6 +41,7 @@ properties: - qcom,sm8450-ufshc - qcom,sm8550-ufshc - qcom,sm8650-ufshc + - qcom,x1e80100-ufshc - const: qcom,ufshc - const: jedec,ufs-2.0 =20 @@ -121,6 +122,7 @@ allOf: contains: enum: - qcom,sc7180-ufshc + - qcom,x1e80100-ufshc then: properties: clocks: --=20 2.39.2 From nobody Tue Feb 10 09:30:46 2026 Received: from gollum.nazgul.ch (gollum.nazgul.ch [81.221.21.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B27820E6; Sat, 17 Aug 2024 07:12:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.221.21.253 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878733; cv=none; b=oNONpA7RVanqN7TNDguMJbJ2qwcoHtgdRRrd/bFdKrSOkqkpuZnn0w4H9wbI0stKUW9+drKGRT/I98vpqgpnsMO4PSWpLz4VgSYAUASStwLfPGTB6ToLVF1nwRJoBt5o2N9KPvnShrww6cR+UfgkLFttcbS8l7LHBl57eZgv01o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878733; c=relaxed/simple; bh=RUP6Gqoj9OT0gB/mLdkcHmKdOD4LZB/wGNIcRzaeELo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hXDdqPKmEjJioFX9sZPbKOF3r++L3MJsonG6aGSWCbHSa4AEgMNzsSN45VYK2HiR3yekhFSsL1uP584AKSBoX8IoyosHhGU6YxWa0w2G6sLth15CCysy2tQZ3pWUH2+VIcCETKStqHmENj+3+JoWSJJpmzo1YkAXkR3Da2czJvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch; spf=pass smtp.mailfrom=nazgul.ch; arc=none smtp.client-ip=81.221.21.253 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nazgul.ch Received: from localhost (gollum.nazgul.ch [local]) by gollum.nazgul.ch (OpenSMTPD) with ESMTPA id 45b17932; Sat, 17 Aug 2024 09:12:09 +0200 (CEST) Date: Sat, 17 Aug 2024 09:12:09 +0200 From: Marcus Glocker To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Konrad Dybcio Subject: [PATCH v4 4/6] arm64: dts: qcom: Add UFS node Message-ID: References: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the ufs host controller node for the Qualcomm X1E80100. This was copied from arch/arm64/boot/dts/qcom/sc7180.dtsi and adapted to our needs. Signed-off-by: Marcus Glocker --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 71 ++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 7bca5fcd7d52..235e20e4b51f 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2878,6 +2878,77 @@ mmss_noc: interconnect@1780000 { #interconnect-cells =3D <2>; }; =20 + ufs_mem_hc: ufs@1d84000 { + compatible =3D "qcom,x1e80100-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg =3D <0 0x01d84000 0 0x3000>; + interrupts =3D ; + phys =3D <&ufs_mem_phy>; + phy-names =3D "ufsphy"; + lanes-per-direction =3D <1>; + #reset-cells =3D <1>; + resets =3D <&gcc GCC_UFS_PHY_BCR>; + reset-names =3D "rst"; + + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + + iommus =3D <&apps_smmu 0xa0 0x0>; + + clock-names =3D "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk"; + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; + freq-table-hz =3D <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <0 0>, + <0 0>, + <0 0>; + + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "ufs-ddr", "cpu-ufs"; + + qcom,ice =3D <&ice>; + + status =3D "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible =3D "qcom,x1e80100-qmp-ufs-phy"; + reg =3D <0 0x01d87000 0 0x1000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names =3D "ref", + "ref_aux", + "qref"; + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + resets =3D <&ufs_mem_hc 0>; + reset-names =3D "ufsphy"; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + ice: crypto@1d90000 { + compatible =3D "qcom,x1e80100-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg =3D <0 0x01d90000 0 0x8000>; + clocks =3D <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + pcie6a: pci@1bf8000 { device_type =3D "pci"; compatible =3D "qcom,pcie-x1e80100"; --=20 2.39.2 From nobody Tue Feb 10 09:30:46 2026 Received: from gollum.nazgul.ch (gollum.nazgul.ch [81.221.21.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A8B2913D2A9; Sat, 17 Aug 2024 07:13:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.221.21.253 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878799; cv=none; b=cj/GHLT7wEhzeg53dc5rajsSp9+JDSp65lsZ6ksMcEqeBbmvlSwfoG0Q4Ec1QwkymhH4eiC3QNJRRqtqYekXLQpenDF4ZbHmp6JNrwrKiquZIlqfFEnWfrWDtTVPrDgPPFf3oXAn4od//Oe/d0JJslnTZywW9wWzSqEJ7TON8jA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723878799; c=relaxed/simple; bh=Q50X+iiAUTtWK/G4L8ENbhYe21kcz7+eUohGKc1ueoU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=B5AutgqySiv50L8PIdGfO9Vbsmuyj+5lPufrjnYKV9BQhPEY6iYFjd7YlRzR4HiimN4Lm7p2ipuYKvEK1YZeGA9I8Rbxr7kIz5oamGOT3hq9nokxU3aQQLYx/5OT7Ir5gNujMR3l6QTLCyeUnsZt0zyl+/hBmbxCKxZo6WVQ7vY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch; spf=pass smtp.mailfrom=nazgul.ch; arc=none smtp.client-ip=81.221.21.253 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nazgul.ch Received: from localhost (gollum.nazgul.ch [local]) by gollum.nazgul.ch (OpenSMTPD) with ESMTPA id 9ea65a6b; Sat, 17 Aug 2024 09:13:15 +0200 (CEST) Date: Sat, 17 Aug 2024 09:13:15 +0200 From: Marcus Glocker To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Konrad Dybcio Subject: [PATCH v4 5/6] dt-bindings: arm: Add Samsung Galaxy Book4 Edge Message-ID: References: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document the Samsung Galaxy Book4 Edge compatible. Signed-off-by: Marcus Glocker --- Documentation/devicetree/bindings/arm/qcom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index f08e13b61172..c8a32e5d2c74 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -1044,6 +1044,7 @@ properties: - lenovo,yoga-slim7x - qcom,x1e80100-crd - qcom,x1e80100-qcp + - samsung,galaxy-book4-edge - const: qcom,x1e80100 =20 # Board compatibles go above --=20 2.39.2 From nobody Tue Feb 10 09:30:46 2026 Received: from gollum.nazgul.ch (gollum.nazgul.ch [81.221.21.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2DFE13CFA3; Sat, 17 Aug 2024 07:17:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=81.221.21.253 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723879058; cv=none; b=tRoqdQwP/xKGlnhnP9gRVnZ5/+Ue/re0aYYfef38D/WlLon6Y24A5GpKea+1ycj/otEbsvQLVGCPLnLNODgkrvF5kXZ+/8kQ83nBY5lVhj6h3A29PNDxIGnfCjilVH47OKpuz52audgzUIyFPbhNIvdWw6OEBLABV8gPQSib5+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723879058; c=relaxed/simple; bh=Kc4H74pzHe5El3Lr0ZHtldcyVSpDI2RpBWOK89wdjXg=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Tz7QSWZzalo3k8VhTw5w0vmYqACb+xBMTLlD94PC0/eBDN82tioF54oXuLKxZKb6dYNz79Pz1IAuhFMHkClVSh3tqTizHkP0Bd4gzSaSG06X0z7Q9kzG/tt9788fKQaRGJH/JO6RCWUehD+qQZ8eiTb3/n/9bnFlwzcvafv9D6A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch; spf=pass smtp.mailfrom=nazgul.ch; arc=none smtp.client-ip=81.221.21.253 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=nazgul.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=nazgul.ch Received: from localhost (gollum.nazgul.ch [local]) by gollum.nazgul.ch (OpenSMTPD) with ESMTPA id 9deb8a4f; Sat, 17 Aug 2024 09:17:34 +0200 (CEST) Date: Sat, 17 Aug 2024 09:17:34 +0200 From: Marcus Glocker To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold , Konrad Dybcio Subject: [PATCH v4 6/6] arm64: dts: qcom: Add Samsung Galaxy Book4 Edge DTS Message-ID: <7ofb7k3vbzuuidtzeqyeiokzxpj5hbclpeungfkpf2yqfiy3s6@zoanfycrqgjs> References: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <3lmcfffifsg6v3ljzxfbk25ydh6446phdff7w75k6gwoyw3jkw@ryc66frtyksk> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the initial DTS file for the Samsung Galaxy Book4 Edge laptop. This was a copy of arch/arm64/boot/dts/qcom/x1e80100-crd.dts and adapted to our needs. Signed-off-by: Marcus Glocker --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../x1e80100-samsung-galaxy-book4-edge.dts | 959 ++++++++++++++++++ 2 files changed, 960 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-= edge.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 0e5c810304fb..77a48a5780ed 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -265,3 +265,4 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-asus-vivobook-s15= .dtb dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-crd.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-lenovo-yoga-slim7x.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-qcp.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D x1e80100-samsung-galaxy-book4-edge.dtb diff --git a/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge.dt= s b/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge.dts new file mode 100644 index 000000000000..484e28d24501 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/x1e80100-samsung-galaxy-book4-edge.dts @@ -0,0 +1,959 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include +#include + +#include "x1e80100.dtsi" +#include "x1e80100-pmics.dtsi" + +/ { + model =3D "Samsung Galaxy Book4 Edge"; + compatible =3D "samsung,galaxy-book4-edge", "qcom,x1e80100"; + chassis-type =3D "laptop"; + + pmic-glink { + compatible =3D "qcom,x1e80100-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 121 GPIO_ACTIVE_HIGH>, + <&tlmm 123 GPIO_ACTIVE_HIGH>, + <&tlmm 125 GPIO_ACTIVE_HIGH>; + + /* Left-side rear port */ + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss0_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + }; + }; + + /* Left-side front port */ + connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss1_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + }; + }; + + /* Right-side port */ + connector@2 { + compatible =3D "usb-c-connector"; + reg =3D <2>; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_ss2_hs_in: endpoint { + remote-endpoint =3D <&usb_1_ss2_dwc3_hs>; + }; + }; + + port@1 { + reg =3D <1>; + + pmic_glink_ss2_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss2_qmpphy_out>; + }; + }; + }; + }; + }; + + reserved-memory { + linux,cma { + compatible =3D "shared-dma-pool"; + size =3D <0x0 0x8000000>; + reusable; + linux,cma-default; + }; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + vreg_edp_3p3: regulator-edp-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_EDP_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 70 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&edp_reg_en>; + pinctrl-names =3D "default"; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm8550-rpmh-regulators"; + qcom,pmic-id =3D "b"; + + vdd-bob1-supply =3D <&vph_pwr>; + vdd-bob2-supply =3D <&vph_pwr>; + vdd-l1-l4-l10-supply =3D <&vreg_s4c_1p8>; + vdd-l2-l13-l14-supply =3D <&vreg_bob1>; + vdd-l5-l16-supply =3D <&vreg_bob1>; + vdd-l6-l7-supply =3D <&vreg_bob2>; + vdd-l8-l9-supply =3D <&vreg_bob1>; + vdd-l12-supply =3D <&vreg_s5j_1p2>; + vdd-l15-supply =3D <&vreg_s4c_1p8>; + vdd-l17-supply =3D <&vreg_bob2>; + + vreg_bob1: bob1 { + regulator-name =3D "vreg_bob1"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + + vreg_bob2: bob2 { + regulator-name =3D "vreg_bob2"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l1b_1p8: ldo1 { + regulator-name =3D "vreg_l1b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name =3D "vreg_l2b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3100000>; + regulator-initial-mode =3D ; + }; + + vreg_l4b_1p8: ldo4 { + regulator-name =3D "vreg_l4b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b_3p0: ldo5 { + regulator-name =3D "vreg_l5b_3p0"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name =3D "vreg_l6b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b_2p8: ldo7 { + regulator-name =3D "vreg_l7b_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b_3p0: ldo8 { + regulator-name =3D "vreg_l8b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name =3D "vreg_l9b_2p9"; + regulator-min-microvolt =3D <2960000>; + regulator-max-microvolt =3D <2960000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b_1p8: ldo10 { + regulator-name =3D "vreg_l10b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b_1p2: ldo12 { + regulator-name =3D "vreg_l12b_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name =3D "vreg_l13b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3100000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b_3p0: ldo14 { + regulator-name =3D "vreg_l14b_3p0"; + regulator-min-microvolt =3D <3072000>; + regulator-max-microvolt =3D <3072000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name =3D "vreg_l15b_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b_2p9: ldo16 { + regulator-name =3D "vreg_l16b_2p9"; + regulator-min-microvolt =3D <2912000>; + regulator-max-microvolt =3D <2912000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name =3D "vreg_l17b_2p5"; + regulator-min-microvolt =3D <2504000>; + regulator-max-microvolt =3D <2504000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "c"; + + vdd-l1-supply =3D <&vreg_s5j_1p2>; + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s4-supply =3D <&vph_pwr>; + + vreg_s4c_1p8: smps4 { + regulator-name =3D "vreg_s4c_1p8"; + regulator-min-microvolt =3D <1856000>; + regulator-max-microvolt =3D <2000000>; + regulator-initial-mode =3D ; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name =3D "vreg_l1c_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l2c_0p8: ldo2 { + regulator-name =3D "vreg_l2c_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l3c_0p8: ldo3 { + regulator-name =3D "vreg_l3c_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "d"; + + vdd-l1-supply =3D <&vreg_s1f_0p7>; + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s4c_1p8>; + vdd-s1-supply =3D <&vph_pwr>; + + vreg_l1d_0p8: ldo1 { + regulator-name =3D "vreg_l1d_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l2d_0p9: ldo2 { + regulator-name =3D "vreg_l2d_0p9"; + regulator-min-microvolt =3D <912000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l3d_1p8: ldo3 { + regulator-name =3D "vreg_l3d_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-3 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "e"; + + vdd-l2-supply =3D <&vreg_s1f_0p7>; + vdd-l3-supply =3D <&vreg_s5j_1p2>; + + vreg_l2e_0p8: ldo2 { + regulator-name =3D "vreg_l2e_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l3e_1p2: ldo3 { + regulator-name =3D "vreg_l3e_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-4 { + compatible =3D "qcom,pmc8380-rpmh-regulators"; + qcom,pmic-id =3D "f"; + + vdd-l1-supply =3D <&vreg_s5j_1p2>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s5j_1p2>; + vdd-s1-supply =3D <&vph_pwr>; + + vreg_s1f_0p7: smps1 { + regulator-name =3D "vreg_s1f_0p7"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1f_1p0: ldo1 { + regulator-name =3D "vreg_l1f_1p0"; + regulator-min-microvolt =3D <1024000>; + regulator-max-microvolt =3D <1024000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f_1p0: ldo2 { + regulator-name =3D "vreg_l2f_1p0"; + regulator-min-microvolt =3D <1024000>; + regulator-max-microvolt =3D <1024000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f_1p0: ldo3 { + regulator-name =3D "vreg_l3f_1p0"; + regulator-min-microvolt =3D <1024000>; + regulator-max-microvolt =3D <1024000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-6 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "i"; + + vdd-l1-supply =3D <&vreg_s4c_1p8>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + + vreg_s1i_0p9: smps1 { + regulator-name =3D "vreg_s1i_0p9"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_s2i_1p0: smps2 { + regulator-name =3D "vreg_s2i_1p0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1100000>; + regulator-initial-mode =3D ; + }; + + vreg_l1i_1p8: ldo1 { + regulator-name =3D "vreg_l1i_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l2i_1p2: ldo2 { + regulator-name =3D "vreg_l2i_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l3i_0p8: ldo3 { + regulator-name =3D "vreg_l3i_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-7 { + compatible =3D "qcom,pm8550ve-rpmh-regulators"; + qcom,pmic-id =3D "j"; + + vdd-l1-supply =3D <&vreg_s1f_0p7>; + vdd-l2-supply =3D <&vreg_s5j_1p2>; + vdd-l3-supply =3D <&vreg_s1f_0p7>; + vdd-s5-supply =3D <&vph_pwr>; + + vreg_s5j_1p2: smps5 { + regulator-name =3D "vreg_s5j_1p2"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1304000>; + regulator-initial-mode =3D ; + }; + + vreg_l1j_0p8: ldo1 { + regulator-name =3D "vreg_l1j_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + + vreg_l2j_1p2: ldo2 { + regulator-name =3D "vreg_l2j_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l3j_0p8: ldo3 { + regulator-name =3D "vreg_l3j_0p8"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <920000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&i2c0 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + keyboard@5 { + compatible =3D "hid-over-i2c"; + reg =3D <0x5>; + + hid-descr-addr =3D <0x20>; + interrupts-extended =3D <&tlmm 67 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 =3D <&kybd_default>; + pinctrl-names =3D "default"; + + wakeup-source; + }; +}; + +&i2c8 { + clock-frequency =3D <400000>; + + status =3D "disabled"; + + touchscreen@5d { + compatible =3D "hid-over-i2c"; + reg =3D <0x5d>; + + hid-descr-addr =3D <0x1>; + /* XXX: Pin 51 is creating an interrupt storm. */ + interrupts-extended =3D <&tlmm 51 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 =3D <&ts0_default>; + pinctrl-names =3D "default"; + }; +}; + +&i2c13 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + touchpad@40 { + compatible =3D "hid-over-i2c"; + reg =3D <0x40>; + + hid-descr-addr =3D <0xe>; + interrupts-extended =3D <&tlmm 3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 =3D <&tpad_default>; + pinctrl-names =3D "default"; + }; +}; + +&lpass_tlmm { + spkr_01_sd_n_active: spkr-01-sd-n-active-state { + pins =3D "gpio12"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; + + spkr_23_sd_n_active: spkr-23-sd-n-active-state { + pins =3D "gpio13"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; +}; + +&lpass_vamacro { + pinctrl-0 =3D <&dmic01_default>, <&dmic23_default>; + pinctrl-names =3D "default"; + + vdd-micb-supply =3D <&vreg_l1b_1p8>; + qcom,dmic-sample-rate =3D <4800000>; +}; + +&mdss { + status =3D "okay"; +}; + +&mdss_dp3 { + compatible =3D "qcom,x1e80100-dp"; + /delete-property/ #sound-dai-cells; + + status =3D "okay"; + + aux-bus { + panel { + compatible =3D "edp-panel"; + power-supply =3D <&vreg_edp_3p3>; + + port { + edp_panel_in: endpoint { + remote-endpoint =3D <&mdss_dp3_out>; + }; + }; + }; + }; + + ports { + port@1 { + reg =3D <1>; + mdss_dp3_out: endpoint { + data-lanes =3D <0 1 2 3>; + link-frequencies =3D + /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; + + remote-endpoint =3D <&edp_panel_in>; + }; + }; + }; +}; + +&mdss_dp3_phy { + vdda-phy-supply =3D <&vreg_l3j_0p8>; + vdda-pll-supply =3D <&vreg_l2j_1p2>; + + status =3D "okay"; +}; + +&pcie4 { + perst-gpios =3D <&tlmm 146 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 148 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&pcie4_default>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie4_phy { + vdda-phy-supply =3D <&vreg_l3i_0p8>; + vdda-pll-supply =3D <&vreg_l3e_1p2>; + + status =3D "okay"; +}; + +&qupv3_0 { + status =3D "okay"; +}; + +&qupv3_1 { + status =3D "okay"; +}; + +&qupv3_2 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/qcadsp8380.mbn= ", + "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/adsp_dtbs.elf"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/qccdsp8380.mbn= ", + "qcom/x1e80100/SAMSUNG/galaxy-book4-edge/cdsp_dtbs.elf"; + + status =3D "okay"; +}; + +&smb2360_0_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l2b_3p0>; +}; + +&smb2360_1_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l14b_3p0>; +}; + +&smb2360_2 { + status =3D "okay"; +}; + +&smb2360_2_eusb2_repeater { + vdd18-supply =3D <&vreg_l3d_1p8>; + vdd3-supply =3D <&vreg_l8b_3p0>; +}; + +&swr0 { + status =3D "okay"; + + pinctrl-0 =3D <&wsa_swr_active>, <&spkr_01_sd_n_active>; + pinctrl-names =3D "default"; + + /* WSA8845, Left Woofer */ + left_woofer: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + reset-gpios =3D <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "WooferLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + }; + + /* WSA8845, Left Tweeter */ + left_tweeter: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + reset-gpios =3D <&lpass_tlmm 12 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TwitterLeft"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + }; +}; + +&swr1 { + status =3D "okay"; + + /* WCD9385 RX */ + wcd_rx: codec@0,4 { + compatible =3D "sdw20217010d00"; + reg =3D <0 4>; + qcom,rx-port-mapping =3D <1 2 3 4 5>; + }; +}; + +&swr2 { + status =3D "okay"; + + /* WCD9385 TX */ + wcd_tx: codec@0,3 { + compatible =3D "sdw20217010d00"; + reg =3D <0 3>; + qcom,tx-port-mapping =3D <2 2 3 4>; + }; +}; + +&swr3 { + status =3D "okay"; + + pinctrl-0 =3D <&wsa2_swr_active>, <&spkr_23_sd_n_active>; + pinctrl-names =3D "default"; + + /* WSA8845, Right Woofer */ + right_woofer: speaker@0,0 { + compatible =3D "sdw20217020400"; + reg =3D <0 0>; + reset-gpios =3D <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "WooferRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + }; + + /* WSA8845, Right Tweeter */ + right_tweeter: speaker@0,1 { + compatible =3D "sdw20217020400"; + reg =3D <0 1>; + reset-gpios =3D <&lpass_tlmm 13 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TwitterRight"; + vdd-1p8-supply =3D <&vreg_l15b_1p8>; + vdd-io-supply =3D <&vreg_l12b_1p2>; + }; +}; + +&tlmm { + gpio-reserved-ranges =3D <34 2>, /* Unused */ + <44 4>, /* SPI (TPM) */ + <238 1>; /* UFS Reset */ + + edp_reg_en: edp-reg-en-state { + pins =3D "gpio70"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; + + kybd_default: kybd-default-state { + pins =3D "gpio67"; + function =3D "gpio"; + bias-disable; + }; + + pcie4_default: pcie4-default-state { + clkreq-n-pins { + pins =3D "gpio147"; + function =3D "pcie4_clk"; + drive-strength =3D <2>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio146"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + wake-n-pins { + pins =3D "gpio148"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + + tpad_default: tpad-default-state { + pins =3D "gpio3"; + function =3D "gpio"; + bias-disable; + }; + + ts0_default: ts0-default-state { + int-n-pins { + pins =3D "gpio51"; + function =3D "gpio"; + bias-disable; + }; + + reset-n-pins { + pins =3D "gpio48"; + function =3D "gpio"; + output-high; + drive-strength =3D <16>; + }; + }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio191"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + output-low; + }; +}; + +&ufs_mem_hc { + status =3D "okay"; + + vcc-supply =3D <&vreg_l9b_2p9>; + vcc-max-microamp =3D <600000>; + vccq2-supply =3D <&vreg_l4b_1p8>; + vccq2-max-microamp =3D <600000>; +}; + +&ufs_mem_phy { + status =3D "okay"; + + vdda-phy-supply =3D <&vreg_l2c_0p8>; + vdda-phy-max-microamp =3D <62900>; + vdda-pll-supply =3D <&vreg_l12b_1p2>; + vdda-pll-max-microamp =3D <18300>; +}; + +&uart21 { + compatible =3D "qcom,geni-debug-uart"; + status =3D "okay"; +}; + +&usb_1_ss0_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_0_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss0_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l1j_0p8>; + + status =3D "okay"; +}; + +&usb_1_ss0 { + status =3D "okay"; +}; + +&usb_1_ss0_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss0_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss0_hs_in>; +}; + +&usb_1_ss0_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; +}; + +&usb_1_ss1_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_1_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss1_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p9>; + + status =3D "okay"; +}; + +&usb_1_ss1 { + status =3D "okay"; +}; + +&usb_1_ss1_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss1_hs_in>; +}; + +&usb_1_ss1_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; +}; + +&usb_1_ss2_hsphy { + vdd-supply =3D <&vreg_l3j_0p8>; + vdda12-supply =3D <&vreg_l2j_1p2>; + + phys =3D <&smb2360_2_eusb2_repeater>; + + status =3D "okay"; +}; + +&usb_1_ss2_qmpphy { + vdda-phy-supply =3D <&vreg_l3e_1p2>; + vdda-pll-supply =3D <&vreg_l2d_0p9>; + + status =3D "okay"; +}; + +&usb_1_ss2 { + status =3D "okay"; +}; + +&usb_1_ss2_dwc3 { + dr_mode =3D "host"; +}; + +&usb_1_ss2_dwc3_hs { + remote-endpoint =3D <&pmic_glink_ss2_hs_in>; +}; + +&usb_1_ss2_qmpphy_out { + remote-endpoint =3D <&pmic_glink_ss2_ss_in>; +}; --=20 2.39.2