From nobody Thu Apr 9 17:24:01 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5865337BE77; Fri, 6 Mar 2026 10:26:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772792798; cv=none; b=o1KC7Yy+AuslXwhqhPpWga9lTxU4HlJEm5W6d2VGvkdJD6BsedWwpLLD7I/yrnuJpUez7mvq9GG7UYr8eD5Da++ZmO8SeIQMxXjRRqHR9xcsbtjodqOdVUQrdPr3yic46/o6s9fDVGXme1okAP3DFQ0UDzt25faTrIjo7pvm1pY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772792798; c=relaxed/simple; bh=s25iVwYLw5FeYXbWrPlYuYFcy6HOsbcylMYHwGmyojc=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=UbOivyTkSjni/ef263HUoV9+ZJPpeApxAQkAwqGCu+qKp64gnafRXJ/ExwcW9v8KWa64DBEOuUrb0gYHP31RGFfh6uASMAET2/1xqDWtxlPC/mq8yOhF0/lb30peRmBI9ufnzaHE+q7pj/H4qdk3t0+T5MJ9UAQZfvm+AOadzHk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3BB4AC19422; Fri, 6 Mar 2026 10:26:36 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v2] dt-bindings: interrupt-controller: arm,gic-v3: Fix EPPI range Date: Fri, 6 Mar 2026 11:26:20 +0100 Message-ID: <3e49a63c6b2b6ee48e3737adee87781f9c136c5f.1772792753.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to the "Arm Generic Interrupt Controller (GIC) Architecture Specification, v3 and v4", revision H.b[1], there can be only 64 Extended PPI interrupts. [1] https://developer.arm.com/documentation/ihi0069/hb/ Fixes: 4b049063e0bcbfd3 ("dt-bindings: interrupt-controller: arm,gic-v3: De= scribe EPPI range support") Signed-off-by: Geert Uytterhoeven Brain-farted-by: Marc Zyngier Acked-by: Marc Zyngier --- v2: - s/v3 and v3/v3 and v4/, - Add tags. --- .../devicetree/bindings/interrupt-controller/arm,gic-v3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= -v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v= 3.yaml index bfd30aae682bf3f7..360a0643a0b567a4 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -50,7 +50,7 @@ properties: The 2nd cell contains the interrupt number for the interrupt type. SPI interrupts are in the range [0-987]. PPI interrupts are in the range [0-15]. Extended SPI interrupts are in the range [0-1023]. - Extended PPI interrupts are in the range [0-127]. + Extended PPI interrupts are in the range [0-63]. =20 The 3rd cell is the flags, encoded as follows: bits[3:0] trigger type and level flags. --=20 2.43.0