From nobody Thu Oct 2 23:53:21 2025 Received: from out198-20.us.a.mail.aliyun.com (out198-20.us.a.mail.aliyun.com [47.90.198.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C604925B2F4; Wed, 10 Sep 2025 03:05:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=47.90.198.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757473531; cv=none; b=A5sg+dCG4axTr8y/+u9GZfVDg3xS9yRzbmmSlU+K+7Bw5ZTj4VBK7+eN8NFT0Qcijo6UYX4kAEfyoaj/q8tJLNzUk/kMD4Pr/rLpg/t93ZjTy+COW3Ksl7ldXPYfjYpJiqZ98kwiS2aU9fU7tFExOD/2ok3fXoWohHgXMuOx6jg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1757473531; c=relaxed/simple; bh=OPf2QR2k6DAiKqVX0oVySRjxE6j2hrfdjMNsYF+M5Xs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fC/Vk1OZkY0ihNrpe4SIYBIvXIapWcQnvkucGqfFbxZ03+vDYRREzL4r36KwTW2r+5/b8gz2hYPw7llcbog1ttaeWcYFrytZcvJFAlCTumctZIDpeXoB/rHr+1wIJZ8mWJbsob5OX5zlTJYYgLBcVUIj79WQV9KtrbbLrJgC1TE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=antgroup.com; spf=pass smtp.mailfrom=antgroup.com; dkim=pass (1024-bit key) header.d=antgroup.com header.i=@antgroup.com header.b=V63k7WyG; arc=none smtp.client-ip=47.90.198.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=antgroup.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=antgroup.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=antgroup.com header.i=@antgroup.com header.b="V63k7WyG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=antgroup.com; s=default; t=1757473514; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=E93cY9FHGBGF8PLSftp1VfXTr3kQA09+IbltBz6T4yc=; b=V63k7WyG1wUTbdCfT7qVAta4EaGh01O9+eyOwslzy6DaWNpodzj4qOcmDF7XdCkdK2RpdfYxlw36TG05AW0tZUt2jN9F6IJrWMUMaHXUL/ZYKjY1UBRZ0dcVfZyxX2uDGR0Q+AZveTJFbmGHH+3e/pe/DrnMHmj4oXWNDEfeWn4= Received: from localhost(mailfrom:houwenlong.hwl@antgroup.com fp:SMTPD_---.ebeulmh_1757472571 cluster:ay29) by smtp.aliyun-inc.com; Wed, 10 Sep 2025 10:49:31 +0800 From: Hou Wenlong To: kvm@vger.kernel.org Cc: Lai Jiangshan , Sean Christopherson , Paolo Bonzini , Shuah Khan , linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] KVM: selftests: Verify 'BS' bit checking in pending debug exception during VM entry Date: Wed, 10 Sep 2025 10:49:19 +0800 Message-Id: <3c0686934fc33ebb484aa5cc71443a22504df7ca.1757416809.git.houwenlong.hwl@antgroup.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the x86's debug_regs test, add a test case to cover the scenario where single-step with STI in VMX sets the 'BS' bit in pending debug exceptions for #DB interception and instruction emulation in both cases. Signed-off-by: Hou Wenlong --- .../selftests/kvm/include/x86/processor.h | 3 +- tools/testing/selftests/kvm/x86/debug_regs.c | 41 +++++++++++++++++-- 2 files changed, 40 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 488d516c4f6f..f5827cca813e 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -34,7 +34,8 @@ extern uint64_t guest_tsc_khz; =20 #define NMI_VECTOR 0x02 =20 -#define X86_EFLAGS_FIXED (1u << 1) +#define X86_EFLAGS_FIXED (1u << 1) +#define X86_EFLAGS_TF (1u << 8) =20 #define X86_CR4_VME (1ul << 0) #define X86_CR4_PVI (1ul << 1) diff --git a/tools/testing/selftests/kvm/x86/debug_regs.c b/tools/testing/s= elftests/kvm/x86/debug_regs.c index ba80b77c2869..60dea0116b21 100644 --- a/tools/testing/selftests/kvm/x86/debug_regs.c +++ b/tools/testing/selftests/kvm/x86/debug_regs.c @@ -15,11 +15,31 @@ =20 #define IRQ_VECTOR 0xAA =20 +#define CAST_TO_RIP(v) ((unsigned long long)&(v)) + /* For testing data access debug BP */ uint32_t guest_value; =20 extern unsigned char sw_bp, hw_bp, write_data, ss_start, bd_start; -extern unsigned char fep_bd_start; +extern unsigned char fep_bd_start, fep_sti_start, fep_sti_end; + +static void guest_db_handler(struct ex_regs *regs) +{ + static int count; + unsigned long target_rips[2] =3D { + CAST_TO_RIP(fep_sti_start), + CAST_TO_RIP(fep_sti_end), + }; + + __GUEST_ASSERT(regs->rip =3D=3D target_rips[count], "STI: unexpected rip = 0x%lx (should be 0x%lx)", + regs->rip, target_rips[count]); + regs->rflags &=3D ~X86_EFLAGS_TF; + count++; +} + +static void guest_irq_handler(struct ex_regs *regs) +{ +} =20 static void guest_code(void) { @@ -69,13 +89,25 @@ static void guest_code(void) if (is_forced_emulation_enabled) { /* DR6.BD test for emulation */ asm volatile(KVM_FEP "fep_bd_start: mov %%dr0, %%rax" : : : "rax"); + + /* pending debug exceptions for emulation */ + asm volatile("pushf\n\t" + "orq $" __stringify(X86_EFLAGS_TF) ", (%rsp)\n\t" + "popf\n\t" + "sti\n\t" + "fep_sti_start:" + "cli\n\t" + "pushf\n\t" + "orq $" __stringify(X86_EFLAGS_TF) ", (%rsp)\n\t" + "popf\n\t" + KVM_FEP "sti\n\t" + "fep_sti_end:" + "cli\n\t"); } =20 GUEST_DONE(); } =20 -#define CAST_TO_RIP(v) ((unsigned long long)&(v)) - static void vcpu_skip_insn(struct kvm_vcpu *vcpu, int insn_len) { struct kvm_regs regs; @@ -110,6 +142,9 @@ int main(void) vm =3D vm_create_with_one_vcpu(&vcpu, guest_code); run =3D vcpu->run; =20 + vm_install_exception_handler(vm, DB_VECTOR, guest_db_handler); + vm_install_exception_handler(vm, IRQ_VECTOR, guest_irq_handler); + /* Test software BPs - int3 */ memset(&debug, 0, sizeof(debug)); debug.control =3D KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; --=20 2.31.1