From nobody Fri Apr 10 02:39:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DB3D36492C; Wed, 4 Mar 2026 17:11:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644289; cv=none; b=VEfIfDpnjBOhbk3czWcbr5OLbuy2pYg12Iu9gnqX62HOOkNOR3pArlvbixyPVMbkvO1G7xcjLwjtxK5T8m6mLn3+3w9vIxoALiY6m/l7V96Hx84XNvCBE2KDEoNeWJmZw25FiDh6cHzYidJQOgVOXohYvnLf/WllqiH5zaL9RsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644289; c=relaxed/simple; bh=0flkI5uS6bxY1FmU/8NHW+sc//8LjR7RysTF5zqpdkU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lusQvdJomPGEOUnvlA5Wt3oOc7kh9AZR2Ub4j1MmkdrTpv0cDXWowNGeZJCei/SU3clToz+Jlp2Si64uC0AJNoDMjKkQKIWobTlWApE7syy6hqG6cpE09/2cs/Dg+ZFUp35mXMRB+iXfB7OkxnSuxeiaOdbIGMM+nvHjedVP7nY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 46518C2BCB1; Wed, 4 Mar 2026 17:11:24 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 3/7] arm64: dts: fsl-ls1028a: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:11:00 +0100 Message-ID: <3931799d7337d63af505d563754ab784b217a85a.1772643434.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/bo= ot/dts/freescale/fsl-ls1028a.dtsi index e7f9c9319319a69d..f4ba3d16ab86d660 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -114,14 +114,10 @@ optee: optee { =20 timer { compatible =3D "arm,armv8-timer"; - interrupts =3D , - , - , - ; + interrupts =3D , + , + , + ; }; =20 pmu { @@ -138,8 +134,7 @@ gic: interrupt-controller@6000000 { <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ #interrupt-cells =3D <3>; interrupt-controller; - interrupts =3D ; + interrupts =3D ; its: msi-controller@6020000 { compatible =3D "arm,gic-v3-its"; msi-controller; --=20 2.43.0