From nobody Wed Oct 1 23:35:10 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72DB73043C8; Thu, 25 Sep 2025 15:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758815287; cv=none; b=PBiblx1dEdr8SUZtWsZfRtbd72CRCBy7974CIUzpRYKCCXeEpXU5xOMN4jxIBSxxqSLQMkNmbYBwbiwjbvacQdI/UBqDjJKyuuazPSiDeuHT14K7sa01ZOW8Q5t3uyvSq89SFmj0yQEnbP8npVXlVtddlVk+o6fEAXWcdnMkRbY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758815287; c=relaxed/simple; bh=IjHqcP+tfTKbtRDj+etlmWk5c8fXs0oldILjBTpHqn0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=idbz/5NDDTaOYktyZcoR1RSt/mOInRD9J3sUJ0d0iYBo22X8n3RqJTCdhKJy3xStmUKNkFos6WgTZa5sBxKb6+TOLQZf337F4RjokiRZXdVQ5XkIaOnvbNh7HlkhFaUiuc5fCoAiDNeLMe9r5hDIuB2JgYCkq8pJbABuRr+jl0Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GmnUukSv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GmnUukSv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A2B19C4CEF5; Thu, 25 Sep 2025 15:48:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758815287; bh=IjHqcP+tfTKbtRDj+etlmWk5c8fXs0oldILjBTpHqn0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GmnUukSvnxM5e5X/6mrcfpWCnesEheSf7qb5OqG4Na8njDhwm9MyI7+Woe7zlZy4G Phd88cmY6rD/NANadylXCuuX1kkYp1dB+UjhMjnAhDIObkAK773+qpSrTWb83tu4BH u6M07ldiU9hc6ulkVltwLM8nsp5fS1gVNfy71LNXU0bQ2JlnyLT9xeJBVs3n5vrIVn 3Kf0GJ1fk3rdG08hC7ezs/O/pc/BoYk2EzFdLiiZxR0I5lIlOoAuLCy1Wvo54VDUW2 pQWLdbL09krjhpT7RrD/Jmd1+jCtsnx4oZ6iWH1aOHmYpN0u+VamcZlWdsmlN2fKGw ABN59Rr5B2GFA== From: "Rafael J. Wysocki" To: Linux PM Cc: Shawn Guo , Qais Yousef , LKML , Viresh Kumar , Prashanth Prakash , Pierre Gondois , Mario Limonciello , Linux ACPI Subject: [PATCH v1 3/4] ACPI: CPPC: Replace CPUFREQ_ETERNAL with CPPC-specific symbol Date: Thu, 25 Sep 2025 17:46:27 +0200 Message-ID: <3925838.kQq0lBPeGt@rafael.j.wysocki> Organization: Linux Kernel Development In-Reply-To: <8605612.T7Z3S40VBb@rafael.j.wysocki> References: <8605612.T7Z3S40VBb@rafael.j.wysocki> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rafael J. Wysocki Instead of using CPUFREQ_ETERNAL for signaling error conditions in cppc_get_transition_latency(), introduce CPPC_NO_DATA specifically for this purpose and update all of the callers of this function to use it. Signed-off-by: Rafael J. Wysocki --- drivers/acpi/cppc_acpi.c | 6 +++--- drivers/cpufreq/amd-pstate.c | 4 ++-- drivers/cpufreq/cppc_cpufreq.c | 2 +- include/acpi/cppc_acpi.h | 4 +++- include/linux/cpufreq.h | 3 --- 5 files changed, 9 insertions(+), 10 deletions(-) --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1897,16 +1897,16 @@ unsigned int cppc_get_transition_latency =20 cpc_desc =3D per_cpu(cpc_desc_ptr, cpu_num); if (!cpc_desc) - return CPUFREQ_ETERNAL; + return CPPC_NO_DATA; =20 desired_reg =3D &cpc_desc->cpc_regs[DESIRED_PERF]; if (CPC_IN_SYSTEM_MEMORY(desired_reg) || CPC_IN_SYSTEM_IO(desired_reg)) return 0; else if (!CPC_IN_PCC(desired_reg)) - return CPUFREQ_ETERNAL; + return CPPC_NO_DATA; =20 if (pcc_ss_id < 0) - return CPUFREQ_ETERNAL; + return CPPC_NO_DATA; =20 pcc_ss_data =3D pcc_data[pcc_ss_id]; if (pcc_ss_data->pcc_mpar) --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -875,7 +875,7 @@ static u32 amd_pstate_get_transition_del u32 transition_delay_ns; =20 transition_delay_ns =3D cppc_get_transition_latency(cpu); - if (transition_delay_ns =3D=3D CPUFREQ_ETERNAL) { + if (transition_delay_ns =3D=3D CPPC_NO_DATA) { if (cpu_feature_enabled(X86_FEATURE_AMD_FAST_CPPC)) return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY; else @@ -894,7 +894,7 @@ static u32 amd_pstate_get_transition_lat u32 transition_latency; =20 transition_latency =3D cppc_get_transition_latency(cpu); - if (transition_latency =3D=3D CPUFREQ_ETERNAL) + if (transition_latency =3D=3D CPPC_NO_DATA) return AMD_PSTATE_TRANSITION_LATENCY; =20 return transition_latency; --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -312,7 +312,7 @@ static unsigned int get_transition_laten { unsigned int transition_latency_ns =3D cppc_get_transition_latency(cpu); =20 - if (transition_latency_ns =3D=3D CPUFREQ_ETERNAL) + if (transition_latency_ns =3D=3D CPPC_NO_DATA) return CPUFREQ_DEFAULT_TRANSITION_LATENCY_NS / NSEC_PER_USEC; =20 return transition_latency_ns / NSEC_PER_USEC; --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -41,6 +41,8 @@ =20 #define CPPC_ENERGY_PERF_MAX (0xFF) =20 +#define CPPC_NO_DATA (unsigned int)(-1) + /* Each register has the folowing format. */ struct cpc_reg { u8 descriptor; @@ -218,7 +220,7 @@ static inline bool cppc_allow_fast_switc } static inline unsigned int cppc_get_transition_latency(int cpu) { - return CPUFREQ_ETERNAL; + return CPPC_NO_DATA; } static inline bool cpc_ffh_supported(void) {