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Thu, 19 Mar 2026 12:52:08 -0700 From: Nicolin Chen To: , CC: , , , , , , , , , Subject: [PATCH v4 05/10] iommu/arm-smmu-v3: Pass in IOTLB cache tag to CD and STE Date: Thu, 19 Mar 2026 12:51:51 -0700 Message-ID: <3910bdf4c376591c607184db72b3c0adc54f3b17.1773949042.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CF:EE_|CH3PR12MB9025:EE_ X-MS-Office365-Filtering-Correlation-Id: b6287ce8-2357-4038-5a33-08de85f10c3a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|7416014|376014|82310400026|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: GADSGUQLF1RD0ePg0QzEyw+njxbqIUqTViVuNevo6vP9OwmrXGKdYsmhk+SkSwZH2yhJYfYaL2gkPVnf+IJUzPH7eUxhKAI61CQRjeuXeR7dBekAFKvvbhxk8kJwp4Ajk3m6X+NUJBva9ndjW8sNsbN10mcC9MJgRkmXL/iuBk+BH2KuaA3piQO3uyF0K6Za0m3gPIbrCDW8uOzZuDR6IubiT1VGmqoGRNwIXsFkatuSrunEbbBbFA6y8lxdjRTOoP+VxPLyGvu3kE+4axn/mkAr5wZ/Ws544dc6K9DZ7hpy8uaXduE8Ev8+/b/y4qMsmcMEwDZRWUBev0jMOOQysPbkPvNHSMKzOsVjLjLOLnZWge+/Jz2Go9MQXMe72rklZTcBgJmrpkI4XwnEGUWeqiAnaiz9TSRw6YyztzjXMo84nCzZa5KQBpDOq8PFGrSX4glbkQEblkK+kBr5JmB5Zo1bE8ZWP0orXuUPJiGYzIvMpAJrEMP19dnwoeFc0mPF8VydtIYSeIFEuF5xPiW2rOoWIhtKPDoHeC90q/U9qiorLltbL4YtMjx067sNE82omfztFFUkG0WdSD8n7YNBfDo6HHmm4rS+VqONg8WMyjS4fL741vise6Ny/kue36PBvqtAjJ14ddqorXdxes/TCp7mZK8ZKBYREpM1FqqKVoCWCFJPN/NMOdpBiS9FPHfYgP2KtccAvAnSAXp7E1boHW1AO+oXJbkTvsVlBFkh6Q9xvTYt+x3l0yuDyJ8kpmy2dXvb1hgFnQbkJd2G8WptWw== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(7416014)(376014)(82310400026)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; 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charset="utf-8" Now, struct arm_smmu_attach_state has the IOTLB cache tags. Pass them down to arm_smmu_make_s1_cd() and arm_smmu_make_s2_domain_ste() to set in the CD and STE, removing the uses of smmu_domain for ASID/VMID. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 8 +++--- .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 26 ++++++++++++------- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 23 +++++++++++----- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 12 +++++++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 21 +++++++++------ 5 files changed, 61 insertions(+), 29 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 7f86be3144805..385dc76bc1b9f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1010,7 +1010,7 @@ void arm_smmu_make_abort_ste(struct arm_smmu_ste *tar= get); void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, - bool ats_enabled); + struct arm_smmu_inv *tag, bool ats_enabled); =20 #if IS_ENABLED(CONFIG_KUNIT) void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits); @@ -1076,14 +1076,16 @@ struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_= smmu_master *master, u32 ssid); void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain); + struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag); void arm_smmu_write_cd_entry(struct arm_smmu_master *master, int ssid, struct arm_smmu_cd *cdptr, const struct arm_smmu_cd *target); =20 typedef void (*arm_smmu_make_cd_fn)(struct arm_smmu_cd *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain); + struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag); =20 int arm_smmu_set_pasid(struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, ioasid_t pasid, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index ddae0b07c76b5..a77c60321203c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -39,12 +39,15 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, return info; } =20 -static void arm_smmu_make_nested_cd_table_ste( - struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) +static void +arm_smmu_make_nested_cd_table_ste(struct arm_smmu_ste *target, + struct arm_smmu_master *master, + struct arm_smmu_nested_domain *nested_domain, + struct arm_smmu_inv *tag, bool ats_enabled) { - arm_smmu_make_s2_domain_ste( - target, master, nested_domain->vsmmu->s2_parent, ats_enabled); + arm_smmu_make_s2_domain_ste(target, master, + nested_domain->vsmmu->s2_parent, tag, + ats_enabled); =20 target->data[0] =3D cpu_to_le64(STRTAB_STE_0_V | FIELD_PREP(STRTAB_STE_0_CFG, @@ -64,9 +67,11 @@ static void arm_smmu_make_nested_cd_table_ste( * - Bypass STE (install the S2, no CD table) * - CD table STE (install the S2 and the userspace CD table) */ -static void arm_smmu_make_nested_domain_ste( - struct arm_smmu_ste *target, struct arm_smmu_master *master, - struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) +static void +arm_smmu_make_nested_domain_ste(struct arm_smmu_ste *target, + struct arm_smmu_master *master, + struct arm_smmu_nested_domain *nested_domain, + struct arm_smmu_inv *tag, bool ats_enabled) { unsigned int cfg =3D FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(nested_domain->ste[0])); @@ -82,12 +87,12 @@ static void arm_smmu_make_nested_domain_ste( switch (cfg) { case STRTAB_STE_0_CFG_S1_TRANS: arm_smmu_make_nested_cd_table_ste(target, master, nested_domain, - ats_enabled); + tag, ats_enabled); break; case STRTAB_STE_0_CFG_BYPASS: arm_smmu_make_s2_domain_ste(target, master, nested_domain->vsmmu->s2_parent, - ats_enabled); + tag, ats_enabled); break; case STRTAB_STE_0_CFG_ABORT: default: @@ -187,6 +192,7 @@ static int arm_smmu_attach_dev_nested(struct iommu_doma= in *domain, } =20 arm_smmu_make_nested_domain_ste(&ste, master, nested_domain, + &state.new_domain_invst.tag, state.ats_enabled); arm_smmu_install_ste_for_dev(master, &ste); arm_smmu_attach_commit(&state); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iomm= u/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 4370cb88c57cf..846a278fa5469 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -24,12 +24,18 @@ arm_smmu_update_s1_domain_cd_entry(struct arm_smmu_doma= in *smmu_domain) list_for_each_entry(master_domain, &smmu_domain->devices, devices_elm) { struct arm_smmu_master *master =3D master_domain->master; struct arm_smmu_cd *cdptr; + struct arm_smmu_inv tag; =20 cdptr =3D arm_smmu_get_cd_ptr(master, master_domain->ssid); if (WARN_ON(!cdptr)) continue; =20 - arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + if (WARN_ON(arm_smmu_find_iotlb_tag(&smmu_domain->domain, + master->smmu, &tag))) + continue; + if (WARN_ON(tag.type !=3D INV_TYPE_S1_ASID)) + continue; + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain, &tag); arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr, &target_cd); } @@ -124,10 +130,10 @@ EXPORT_SYMBOL_IF_KUNIT(__arm_smmu_make_sva_cd); =20 static void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain) + struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag) { - __arm_smmu_make_sva_cd(target, master, smmu_domain->domain.mm, - smmu_domain->cd.asid); + __arm_smmu_make_sva_cd(target, master, smmu_domain->domain.mm, tag->id); } =20 static void arm_smmu_mm_arch_invalidate_secondary_tlbs(struct mmu_notifier= *mn, @@ -166,12 +172,17 @@ static void arm_smmu_mm_release(struct mmu_notifier *= mn, struct mm_struct *mm) struct arm_smmu_master *master =3D master_domain->master; struct arm_smmu_cd target; struct arm_smmu_cd *cdptr; + struct arm_smmu_inv tag; =20 cdptr =3D arm_smmu_get_cd_ptr(master, master_domain->ssid); if (WARN_ON(!cdptr)) continue; - __arm_smmu_make_sva_cd(&target, master, NULL, - smmu_domain->cd.asid); + if (WARN_ON(arm_smmu_find_iotlb_tag(&smmu_domain->domain, + master->smmu, &tag))) + continue; + if (WARN_ON(tag.type !=3D INV_TYPE_S1_ASID)) + continue; + __arm_smmu_make_sva_cd(&target, master, NULL, tag.id); arm_smmu_write_cd_entry(master, master_domain->ssid, cdptr, &target); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 546138f1efb1b..590bba5acc97e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -347,6 +347,9 @@ static void arm_smmu_test_make_s2_ste(struct arm_smmu_s= te *ste, struct arm_smmu_domain smmu_domain =3D { .pgtbl_ops =3D &io_pgtable.ops, }; + struct arm_smmu_inv tag =3D { + .type =3D INV_TYPE_S2_VMID, + }; =20 io_pgtable.cfg.arm_lpae_s2_cfg.vttbr =3D 0xdaedbeefdeadbeefULL; io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.ps =3D 1; @@ -357,7 +360,8 @@ static void arm_smmu_test_make_s2_ste(struct arm_smmu_s= te *ste, io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.sl =3D 3; io_pgtable.cfg.arm_lpae_s2_cfg.vtcr.tsz =3D 4; =20 - arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, ats_enabled); + arm_smmu_make_s2_domain_ste(ste, &master, &smmu_domain, &tag, + ats_enabled); } =20 static void arm_smmu_v3_write_ste_test_s2_to_abort(struct kunit *test) @@ -502,6 +506,10 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_c= d *cd, unsigned int asid) .asid =3D asid, }, }; + struct arm_smmu_inv tag =3D { + .type =3D INV_TYPE_S1_ASID, + .id =3D asid, + }; =20 io_pgtable.cfg.arm_lpae_s1_cfg.ttbr =3D 0xdaedbeefdeadbeefULL; io_pgtable.cfg.arm_lpae_s1_cfg.tcr.ips =3D 1; @@ -512,7 +520,7 @@ static void arm_smmu_test_make_s1_cd(struct arm_smmu_cd= *cd, unsigned int asid) io_pgtable.cfg.arm_lpae_s1_cfg.tcr.tsz =3D 4; io_pgtable.cfg.arm_lpae_s1_cfg.mair =3D 0xabcdef012345678ULL; =20 - arm_smmu_make_s1_cd(cd, &master, &smmu_domain); + arm_smmu_make_s1_cd(cd, &master, &smmu_domain, &tag); } =20 static void arm_smmu_v3_write_cd_test_s1_clear(struct kunit *test) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 9c23beb8a2545..ca7628abef5bd 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1692,14 +1692,16 @@ void arm_smmu_write_cd_entry(struct arm_smmu_master= *master, int ssid, =20 void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, struct arm_smmu_master *master, - struct arm_smmu_domain *smmu_domain) + struct arm_smmu_domain *smmu_domain, + struct arm_smmu_inv *tag) { - struct arm_smmu_ctx_desc *cd =3D &smmu_domain->cd; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr =3D &pgtbl_cfg->arm_lpae_s1_cfg.tcr; =20 + WARN_ON(tag->type !=3D INV_TYPE_S1_ASID); + memset(target, 0, sizeof(*target)); =20 target->data[0] =3D cpu_to_le64( @@ -1719,7 +1721,7 @@ void arm_smmu_make_s1_cd(struct arm_smmu_cd *target, CTXDESC_CD_0_R | CTXDESC_CD_0_A | CTXDESC_CD_0_ASET | - FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) + FIELD_PREP(CTXDESC_CD_0_ASID, tag->id) ); =20 /* To enable dirty flag update, set both Access flag and dirty state upda= te */ @@ -1976,9 +1978,8 @@ EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_domain *smmu_domain, - bool ats_enabled) + struct arm_smmu_inv *tag, bool ats_enabled) { - struct arm_smmu_s2_cfg *s2_cfg =3D &smmu_domain->s2_cfg; const struct io_pgtable_cfg *pgtbl_cfg =3D &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr =3D @@ -1986,6 +1987,8 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, u64 vtcr_val; struct arm_smmu_device *smmu =3D master->smmu; =20 + WARN_ON(tag->type !=3D INV_TYPE_S2_VMID); + memset(target, 0, sizeof(*target)); target->data[0] =3D cpu_to_le64( STRTAB_STE_0_V | @@ -2009,7 +2012,7 @@ void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste = *target, FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); target->data[2] =3D cpu_to_le64( - FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | + FIELD_PREP(STRTAB_STE_2_S2VMID, tag->id) | FIELD_PREP(STRTAB_STE_2_VTCR, vtcr_val) | STRTAB_STE_2_S2AA64 | #ifdef __BIG_ENDIAN @@ -3772,7 +3775,8 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, case ARM_SMMU_DOMAIN_S1: { struct arm_smmu_cd target_cd; =20 - arm_smmu_make_s1_cd(&target_cd, master, smmu_domain); + arm_smmu_make_s1_cd(&target_cd, master, smmu_domain, + &state.new_domain_invst.tag); arm_smmu_write_cd_entry(master, IOMMU_NO_PASID, cdptr, &target_cd); arm_smmu_make_cdtable_ste(&target, master, state.ats_enabled, @@ -3782,6 +3786,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, } case ARM_SMMU_DOMAIN_S2: arm_smmu_make_s2_domain_ste(&target, master, smmu_domain, + &state.new_domain_invst.tag, state.ats_enabled); arm_smmu_install_ste_for_dev(master, &target); arm_smmu_clear_cd(master, IOMMU_NO_PASID); @@ -3874,7 +3879,7 @@ int arm_smmu_set_pasid(struct arm_smmu_master *master, if (ret) goto out_unlock; =20 - make_cd_fn(cd, master, smmu_domain); + make_cd_fn(cd, master, smmu_domain, &state.new_domain_invst.tag); arm_smmu_write_cd_entry(master, pasid, cdptr, cd); arm_smmu_update_ste(master, sid_domain, state.ats_enabled); =20 --=20 2.43.0