From nobody Fri Apr 10 04:17:46 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B4AC373C0E; Wed, 4 Mar 2026 17:11:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644284; cv=none; b=TdmDH6b8+qW6E0rKyEbUhH6gsxAlLt/Oo/DsElrsZ/GykZESTTfRawKw0Dbjo9Hs4cuzHEjqWdEDye/x71A0xEhYKfo4Xe5Zep66zPuyh9rVGm+aryyBNjx755AE/jEudDIAwWU/EMknXNCGOPL7gEO6Xyf0nIlkHrZLmo69/pE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644284; c=relaxed/simple; bh=/JyfPnWt/dGxBJhxAYz/6x8qmgoIf6ZuWKZPzypnWCQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=e3xNzFiFOpESE9NK8gYORg64u8WcAuWgd9dmZ57jHQ2RFWIK+6aYrRTRf8M7dv1Fz94PKSXDORkvLobYUvGcF/fnou3A3D7ZWIep6Np4D9dGt4TfqdOGzog70k64xil/czW7Twb3cc7aJWS1yowBNoq7Mx47YEyeD+oDRiI73dc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6DF00C2BC9E; Wed, 4 Mar 2026 17:11:19 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Bjorn Andersson , Konrad Dybcio , Thierry Reding Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 2/7] arm64: dts: exynos: gs101: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 4 Mar 2026 18:10:59 +0100 Message-ID: <385def2b0860479dd86cff003f2cececb82dc80f.1772643434.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Unlike older GIC variants, the GICv3 DT bindings do not support specifying a CPU mask in PPI interrupt specifiers. Drop the masks. Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/exynos/google/gs101.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot= /dts/exynos/google/gs101.dtsi index d085f9fb0f62ac2f..2d372d667f79c9d1 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi @@ -1853,10 +1853,10 @@ apm_sram: sram@2039000 { timer { compatible =3D "arm,armv8-timer"; interrupts =3D - , - , - , - ; + , + , + , + ; }; }; =20 --=20 2.43.0