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Mon, 11 Aug 2025 16:00:12 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 5/5] pci: Suspend iommu function prior to resetting a device Date: Mon, 11 Aug 2025 15:59:12 -0700 Message-ID: <3749cd6a1430ac36d1af1fadaa4d90ceffef9c62.1754952762.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022574:EE_|IA0PR12MB8693:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b83d412-f63c-419d-779f-08ddd92ae387 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Au0VMS8kEQrine+KHWf1gjljArI+81XlCUtHJ2i7u/WgTzWpcgZmHOCe/Si4?= =?us-ascii?Q?2CHmXuq0E2uD283G2QMk7APuobJJxfYFep+d4R19cZLUli36pm0ANrFwIN3/?= =?us-ascii?Q?Ab8HBUEOwFiU+4WMT9uRQsIQcZs9ViHAhD5Q0EaxseUvNACBcHpR/tCxbNBW?= =?us-ascii?Q?lblTR3Qs+x2n5NxhS950sLzC4jRTETT+QV8X8RxPlWcor4tPZOV2ftQJ8J0Z?= =?us-ascii?Q?vIC06oltGQ0trANjVt+MXiBnXCxsyUyuuBPO2f6gJ4uR+QWiSfgeBifSaXnM?= =?us-ascii?Q?n6neHvaYHUwZBX89C1UVWh16e7BSwjtvlzFQKztZLVylRhcdXeFmz/I/EiCN?= =?us-ascii?Q?UeEbl6Qf7zWc0+7AEud/cMSVim6H4tEubmliDDiXl10ywUdfh9hc+c6wKH31?= =?us-ascii?Q?xFX09jwNUrnMWDXx505a+SvEYdK5J4Ox3ViyTNs7zphcIv0QJId+vaDreKoO?= =?us-ascii?Q?2ydve5PrDsSczkrWWI3JX6jBRHcNQWBhMX/pyfgncWxcESV/pTnak755HXLV?= =?us-ascii?Q?tQhsyBdSM5I1MGbw5ng2kgisvzwvAZTFSOQvXUmhleF/5Hw7t+Bcjt1bEWR3?= =?us-ascii?Q?5rYkVVeseG5mT1LM9FGl1RqKBIrgHt6htyGbFEJfQ7mKdwEcfPaoipYB/0Uj?= =?us-ascii?Q?/E3oZ2gayT936ULtToVthlYzUhsovx5NsGo/gB9eDOmQIvzXQdLsvGh444DY?= =?us-ascii?Q?MP2vw+xZY3OJnTpr2WOrMJTIse7uzEb4zMu29NLN0GEG985hRpNL6fz6iflJ?= =?us-ascii?Q?FydNiU5iXIPi+l4sCSd5bekDEoAc/qVxiSPxPtrFOXd0WGg1fr6vePq9ZwVl?= =?us-ascii?Q?UWX5gZmK4SCQxwZ+QW2YoBnlmLVjWp1jLxcc54C7XmOnF5FHZpQUj7Xi4Iw4?= =?us-ascii?Q?tKIzsG2SM33h7PdgdDSGZXffoqPdz0V669O9c+ut7NRBEZMASVI8BVXazE0j?= =?us-ascii?Q?Phglnb+/WnrCa/xKDtQ9oB5qKbodT7R9q8RIgwtLB33RebU8aMv77ahKzfWn?= =?us-ascii?Q?BtdHu/2SaOmpMmQZ+lMQBnFQeZpDI1sqoWxUxxeiwoqrjUSe6YDNDhJswxZ6?= =?us-ascii?Q?ObiDdh2qlwpW1Kh7Qil8wOhnbuAN9sPmpADwoFyFFqWz6Wmeqw6LmPmgB35B?= =?us-ascii?Q?L8EiTVPNTePUbwHgPZiF/q51ebSQy2PZmV40f1teOoTXeM9TH2OGacrw6KLO?= =?us-ascii?Q?l9vCwOV0IPTEgA6+aot5sgMpOSO8uSYWTAMjCnrLW2tFVQpsy6190lZzJkZt?= =?us-ascii?Q?yqK60jnOLXv7LqwYvehI2uNP61zjDqNjQ5yTg6YYmvPAVuKXOsXi1iVQSB53?= =?us-ascii?Q?9WdNHFhl59wst5DKEw3RR1R4StJn/hkthFXvT70RWL7OD9ddw5q/TshpKX22?= =?us-ascii?Q?wT0yP3hiGqk+Ij/Swbikqd9q+ZxU8dxxte+DSTbjlXwgubMVeXvsOj9856n7?= =?us-ascii?Q?5yE2HDM+ph02qaJdi/FJehbkPhrAg/mBh2pXTjQjfXQgMj6pHomx0dZf+GJ2?= =?us-ascii?Q?O14877CwI73Dd5Z2dj7FyAImE0LWsxxRM6+Y?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Aug 2025 23:00:38.3750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b83d412-f63c-419d-779f-08ddd92ae387 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022574.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8693 Content-Type: text/plain; charset="utf-8" PCIe permits a device to ignore ATS invalidation TLPs, while processing a reset. This creates a problem visible to the OS where an ATS invalidation command will time out: e.g. an SVA domain will have no coordination with a reset event and can racily issue ATS invalidations to a resetting device. The PCIe spec in sec 10.3.1 IMPLEMENTATION NOTE recommends to disable and block ATS before initiating a Function Level Reset. It also mentions that other reset methods could have the same vulnerability as well. Now iommu_dev_reset_prepare/done() helpers are introduced for this matter. Use them in all the existing reset functions, which will attach the device to an IOMMU_DOMAIN_BLOCKED during a reset, so as to allow IOMMU driver to: - invoke pci_disable_ats() and pci_enable_ats(), if necessary - wait for all ATS invalidations to complete - stop issuing new ATS invalidations - fence any incoming ATS queries Signed-off-by: Nicolin Chen --- drivers/pci/pci-acpi.c | 17 +++++++++-- drivers/pci/pci.c | 68 ++++++++++++++++++++++++++++++++++++++---- drivers/pci/quirks.c | 23 +++++++++++++- 3 files changed, 100 insertions(+), 8 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index ddb25960ea47d..adaf46422c05d 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -969,6 +970,7 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) { acpi_handle handle =3D ACPI_HANDLE(&dev->dev); + int ret =3D 0; =20 if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; @@ -976,12 +978,23 @@ int pci_dev_acpi_reset(struct pci_dev *dev, bool prob= e) if (probe) return 0; =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { pci_warn(dev, "ACPI _RST failed\n"); - return -ENOTTY; + ret =3D -ENOTTY; } =20 - return 0; + iommu_dev_reset_done(&dev->dev); + return ret; } =20 bool acpi_pci_power_manageable(struct pci_dev *dev) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index b0f4d98036cdd..d6d87e22d81b3 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -4529,13 +4530,26 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); */ int pcie_flr(struct pci_dev *dev) { + int ret =3D 0; + if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing func= tion level reset anyway\n"); =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + * Have to call it after waiting for pending DMA transaction. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within @@ -4544,7 +4558,11 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); =20 - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + +done: + iommu_dev_reset_done(&dev->dev); + return ret; } EXPORT_SYMBOL_GPL(pcie_flr); =20 @@ -4572,6 +4590,7 @@ EXPORT_SYMBOL_GPL(pcie_reset_flr); =20 static int pci_af_flr(struct pci_dev *dev, bool probe) { + int ret =3D 0; int pos; u8 cap; =20 @@ -4598,10 +4617,21 @@ static int pci_af_flr(struct pci_dev *dev, bool pro= be) PCI_AF_STATUS_TP << 8)) pci_err(dev, "timed out waiting for pending transaction; performing AF f= unction level reset anyway\n"); =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + * Have to call it after waiting for pending DMA transaction. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, @@ -4611,7 +4641,11 @@ static int pci_af_flr(struct pci_dev *dev, bool prob= e) */ msleep(100); =20 - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + +done: + iommu_dev_reset_done(&dev->dev); + return ret; } =20 /** @@ -4632,6 +4666,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) static int pci_pm_reset(struct pci_dev *dev, bool probe) { u16 csr; + int ret; =20 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4646,6 +4681,16 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) if (dev->current_state !=3D PCI_D0) return -EINVAL; =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + csr &=3D ~PCI_PM_CTRL_STATE_MASK; csr |=3D PCI_D3hot; pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); @@ -4656,7 +4701,9 @@ static int pci_pm_reset(struct pci_dev *dev, bool pro= be) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); =20 - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + iommu_dev_reset_done(&dev->dev); + return ret; } =20 /** @@ -5111,6 +5158,16 @@ static int cxl_reset_bus_function(struct pci_dev *de= v, bool probe) if (rc) return -ENOTTY; =20 + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + */ + rc =3D iommu_dev_reset_prepare(&dev->dev); + if (rc) { + pci_err(dev, "failed to stop IOMMU\n"); + return rc; + } + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) { val =3D reg; } else { @@ -5125,6 +5182,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev= , bool probe) pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, reg); =20 + iommu_dev_reset_done(&dev->dev); return rc; } =20 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index d97335a401930..6157c6c02bdb0 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -21,6 +21,7 @@ #include #include /* isa_dma_bridge_buggy */ #include +#include #include #include #include @@ -4225,6 +4226,26 @@ static const struct pci_dev_reset_methods pci_dev_re= set_methods[] =3D { { 0 } }; =20 +static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, + const struct pci_dev_reset_methods *i) +{ + int ret; + + /* + * Per PCIe r6.3, sec 10.3.1 IMPLEMENTATION NOTE, software disables ATS + * before initiating a reset. Notify the iommu driver that enabled ATS. + */ + ret =3D iommu_dev_reset_prepare(&dev->dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU\n"); + return ret; + } + + ret =3D i->reset(dev, probe); + iommu_dev_reset_done(&dev->dev); + return ret; +} + /* * These device-specific reset methods are here rather than in a driver * because when a host assigns a device to a guest VM, the host may need @@ -4239,7 +4260,7 @@ int pci_dev_specific_reset(struct pci_dev *dev, bool = probe) i->vendor =3D=3D (u16)PCI_ANY_ID) && (i->device =3D=3D dev->device || i->device =3D=3D (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return __pci_dev_specific_reset(dev, probe, i); } =20 return -ENOTTY; --=20 2.43.0