From nobody Fri Apr 10 02:39:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7D64385527; Wed, 4 Mar 2026 17:22:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644936; cv=none; b=DVWgyXtDuu+ET8RPoSgga3Nv3jPOywbWRaq68BocMWh6tvDLcOoaGU25R+ZNQhlgEOjN02uVGP+iZaT8ctttCS2wfvjbmy7JN72FPxTFWR/MucqIO0L5BpHLGE0bf+111GTGpGIUCyrd77E/g6eEhrLFVVpMx/C4AgZbJlt6/MM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772644936; c=relaxed/simple; bh=RaZbaVpjVGmjvfDsydk1VCoQHjEZZ5YVAonjhJxrTxg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pdx2f5VokPsFygKiLin4kDe7v4C4RxoIDRAyrz63eGTqPrXWr/7EXb8xTo5bmd2CKeSyoLZMXWDgGbsIi52BI8h+Hw4ws5Ljk+7yQIlg/xL3/ps3D2x8a4mHBLpfAe4+A7uf1Ikwgu8vtLQJtgYFXHA95UehXrWQzxoqNNRNiVg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id D32E7C2BCB0; Wed, 4 Mar 2026 17:22:09 +0000 (UTC) From: Geert Uytterhoeven To: Marc Zyngier , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Antoine Tenart , Florian Fainelli , Broadcom internal kernel review list , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Mark-PK Tsai , Daniel Palmer , Matthias Brugger , AngeloGioacchino Del Regno , Thierry Reding , Jonathan Hunter , Nishanth Menon , Tero Kristo , Santosh Shilimkar , Kunihiko Hayashi , Masami Hiramatsu Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, imx@lists.linux.dev, linux-amlogic@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-tegra@vger.kernel.org, linux-arm-msm@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH 1/4] dt-bindings: interrupt-controller: arm,gic: Document symbolic definitions Date: Wed, 4 Mar 2026 18:21:56 +0100 Message-ID: <36c8fe02dc911141170ea6607034422410e0ddc2.1772644406.git.geert+renesas@glider.be> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the various GIC DT bindings document the magic GIC and interrupt numbers used in interrupts properties, but omit any references to the corresponding symbolic DT binding definitions. Add references to these symbolic definitions, and convert the examples to make use of them. This improves readability, and makes the examples more similar to what actual users look like. Signed-off-by: Geert Uytterhoeven Reviewed-by: Krzysztof Kozlowski --- .../bindings/interrupt-controller/arm,gic-v3.yaml | 12 +++++++++--- .../interrupt-controller/arm,gic-v5-iwb.yaml | 2 ++ .../bindings/interrupt-controller/arm,gic-v5.yaml | 2 ++ .../bindings/interrupt-controller/arm,gic.yaml | 11 +++++++++-- 4 files changed, 22 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= -v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v= 3.yaml index 360a0643a0b567a4..d1a4b36f06bc3bdb 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -46,6 +46,7 @@ properties: The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI interrupts, 2 for interrupts in the Extended SPI range, 3 for the Extended PPI range. Other values are reserved for future use. + See for symbolic values. =20 The 2nd cell contains the interrupt number for the interrupt type. SPI interrupts are in the range [0-987]. PPI interrupts are in the @@ -56,6 +57,7 @@ properties: bits[3:0] trigger type and level flags. 1 =3D edge triggered 4 =3D level triggered + See for symbolic values. =20 The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node @@ -237,6 +239,8 @@ additionalProperties: false =20 examples: - | + #include + gic: interrupt-controller@2cf00000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <3>; @@ -249,7 +253,7 @@ examples: <0x2c000000 0x2000>, // GICC <0x2c010000 0x2000>, // GICH <0x2c020000 0x2000>; // GICV - interrupts =3D <1 9 4>; + interrupts =3D ; =20 msi-controller; mbi-ranges =3D <256 128>; @@ -263,6 +267,8 @@ examples: }; =20 - | + #include + interrupt-controller@2c010000 { compatible =3D "arm,gic-v3"; #interrupt-cells =3D <4>; @@ -278,7 +284,7 @@ examples: <0x2c040000 0x2000>, // GICC <0x2c060000 0x2000>, // GICH <0x2c080000 0x2000>; // GICV - interrupts =3D <1 9 4 0>; + interrupts =3D ; =20 msi-controller@2c200000 { compatible =3D "arm,gic-v3-its"; @@ -307,7 +313,7 @@ examples: =20 device@0 { reg =3D <0 4>; - interrupts =3D <1 1 4 &part0>; + interrupts =3D ; }; =20 ... diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= -v5-iwb.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,g= ic-v5-iwb.yaml index 99a266a62385a354..3103d314fdcae94c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb= .yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5-iwb= .yaml @@ -46,6 +46,8 @@ properties: 4 =3D active high level-sensitive 8 =3D active low level-sensitive =20 + See for symbolic values. + const: 2 =20 interrupt-controller: true diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= -v5.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v= 5.yaml index 86ca7f3ac2810312..16c66b043210d815 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml @@ -57,6 +57,8 @@ properties: 4 =3D active high level-sensitive 8 =3D active low level-sensitive =20 + See for symbolic values. + const: 3 =20 interrupt-controller: true diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic= .yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index ee4c77dac201ad8f..f05917d0071b5446 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -74,6 +74,7 @@ properties: description: | The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI interrupts. + See for symbolic values. =20 The 2nd cell contains the interrupt number for the interrupt type. SPI interrupts are in the range [0-987]. PPI interrupts are in the @@ -85,6 +86,7 @@ properties: 2 =3D high-to-low edge triggered (invalid for SPIs) 4 =3D active high level-sensitive 8 =3D active low level-sensitive (invalid for SPIs). + See for symbolic values. bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of the 8 possible cpus attached to the GIC. A bit set to '1' indicat= ed the interrupt is wired to that CPU. Only valid for PPI interrupts. @@ -92,6 +94,7 @@ properties: DEFINED and as such not guaranteed to be present (most SoC availab= le in 2014 seem to ignore the setting of this flag and use the hardwa= re default value). + See for symbolic valu= es. =20 reg: description: | @@ -201,6 +204,8 @@ examples: =20 - | // GICv2 + #include + interrupt-controller@2c001000 { compatible =3D "arm,cortex-a15-gic"; #interrupt-cells =3D <3>; @@ -209,18 +214,20 @@ examples: <0x2c002000 0x2000>, <0x2c004000 0x2000>, <0x2c006000 0x2000>; - interrupts =3D <1 9 0xf04>; + interrupts =3D ; }; =20 - | // GICv2m extension for MSI/MSI-x support + #include + interrupt-controller@e1101000 { compatible =3D "arm,gic-400"; #interrupt-cells =3D <3>; #address-cells =3D <1>; #size-cells =3D <1>; interrupt-controller; - interrupts =3D <1 8 0xf04>; + interrupts =3D ; ranges =3D <0 0xe1100000 0x100000>; reg =3D <0xe1110000 0x01000>, <0xe112f000 0x02000>, --=20 2.43.0