From nobody Mon Apr 6 21:56:16 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C57942836A6; Wed, 18 Mar 2026 02:40:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773801627; cv=none; b=gx6g4wpilAWJBMxN7CSjkASlYh5i4NQ6MBF4MmfH49kqSHu7+UFqJxP5M9u48vTZ/G1aDNdd+qKYVdPv56zD1DkOmoa/yd89bkqTg357MjvIp90fpHE/tFbsT/tz25zTQFV8VOg3eJfGrwvSKjEi9myTwmyFY7CpWIyZB6uokjs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773801627; c=relaxed/simple; bh=hJp0Hwkv/zUMQIXKtnF4FC4VYjxIHIdOdrp5NibXHbc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bxFo79STkmBXDGOGM7bWu//tlC2IxI4Ko6BuHiSC94acLX6xhsmvdErrN8cB9+QYXfMKNjyWnr/smPc6nM3aCKa1iaKfr7MtrrmCfWjCWd1HiIF5mKjaSrlLVzvcAdDoUnt/M92yJ8G5RT4jpSLcng1iAgdC3pAt1JS7yaLqw+A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: cbb7b502227311f1a21c59e7364eecb8-20260318 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.11,REQID:978c6859-ceed-4cb1-bc54-43ea149250e1,IP:0,U RL:0,TC:0,Content:-25,EDM:25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:89c9d04,CLOUDID:e90d316a69b4551724c48877068f06c1,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|850|898,TC:nil,Content:0|15|50 ,EDM:5,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OS A:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: cbb7b502227311f1a21c59e7364eecb8-20260318 X-User: xiaopei01@kylinos.cn Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 90819857; Wed, 18 Mar 2026 10:40:15 +0800 From: Pei Xiao To: linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, openbmc@lists.ozlabs.org, linux-rockchip@lists.infradead.org, linux-riscv@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Cc: Pei Xiao Subject: [PATCH v4 12/17] spi: stm32-qspi: Simplify clock handling with devm_clk_get_enabled() Date: Wed, 18 Mar 2026 10:40:02 +0800 Message-Id: <35b4ff674610f77310e84815c15cd59e609c95db.1773801401.git.xiaopei01@kylinos.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace devm_clk_get() followed by clk_prepare_enable() with devm_clk_get_enabled() for the clock. This removes the need for explicit clock enable and disable calls, as the managed API automatically handles clock disabling on device removal or probe failure. Remove the now-unnecessary clk_disable_unprepare() calls from the probe error path and the remove callback. Adjust error labels accordingly. Signed-off-by: Pei Xiao --- drivers/spi/spi-stm32-qspi.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c index df1bbacec90a..a8436f70fdfd 100644 --- a/drivers/spi/spi-stm32-qspi.c +++ b/drivers/spi/spi-stm32-qspi.c @@ -819,25 +819,19 @@ static int stm32_qspi_probe(struct platform_device *p= dev) =20 init_completion(&qspi->match_completion); =20 - qspi->clk =3D devm_clk_get(dev, NULL); + qspi->clk =3D devm_clk_get_enabled(dev, NULL); if (IS_ERR(qspi->clk)) - return PTR_ERR(qspi->clk); - + return dev_err_probe(dev, PTR_ERR(qspi->clk), + "can not enable the clock\n"); qspi->clk_rate =3D clk_get_rate(qspi->clk); if (!qspi->clk_rate) return -EINVAL; =20 - ret =3D clk_prepare_enable(qspi->clk); - if (ret) { - dev_err(dev, "can not enable the clock\n"); - return ret; - } - rstc =3D devm_reset_control_get_exclusive(dev, NULL); if (IS_ERR(rstc)) { ret =3D PTR_ERR(rstc); if (ret =3D=3D -EPROBE_DEFER) - goto err_clk_disable; + goto err_defer; } else { reset_control_assert(rstc); udelay(2); @@ -886,8 +880,7 @@ static int stm32_qspi_probe(struct platform_device *pde= v) pm_runtime_dont_use_autosuspend(qspi->dev); err_dma_free: stm32_qspi_dma_free(qspi); -err_clk_disable: - clk_disable_unprepare(qspi->clk); +err_defer: =20 return ret; } @@ -906,7 +899,6 @@ static void stm32_qspi_remove(struct platform_device *p= dev) pm_runtime_disable(qspi->dev); pm_runtime_set_suspended(qspi->dev); pm_runtime_dont_use_autosuspend(qspi->dev); - clk_disable_unprepare(qspi->clk); } =20 static int stm32_qspi_runtime_suspend(struct device *dev) --=20 2.25.1