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Fri, 25 Oct 2024 16:51:00 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 10/13] iommufd/selftest: Add vIOMMU coverage for IOMMU_HWPT_INVALIDATE ioctl Date: Fri, 25 Oct 2024 16:50:39 -0700 Message-ID: <35452ef0c1bcc9e0ed5217c89c9a72c1f7a17360.1729897278.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|BY5PR12MB4276:EE_ X-MS-Office365-Filtering-Correlation-Id: 7becad32-3c21-454a-ce6b-08dcf54fe5fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?QuNa/mGfQChsSk9MusmIdVCOR4Wpr+hFlb9tNw6eO+5uuQj6oxwwjq+jo4kk?= =?us-ascii?Q?KysXCRuuS4Z9ulg+lI+rU2jD9kQC9xs6KMWHzWqKQYCuzJBrVpVe7/JWQHWp?= =?us-ascii?Q?j9olIgibFzJJlrgqGyTRK3cNlUHN1prk+RHgTkQZ5wJKP+81eSMq0ezAYH8w?= =?us-ascii?Q?fmI3rRJ5lodKtOZXZb7/yE2IqVUIzbKiJceR1noO9LO/p2fvpX1otsLgofOn?= =?us-ascii?Q?Chry3WVKSTGO9rFTxZbMY3iqpUFL6VQ8972oKkFVC+ffixWOQk4bH/Hm/U5I?= =?us-ascii?Q?I3oxeqRomk69Y4/ipU08krLfdSD/1atKBbjLXV5ZaTcgcDmaobaCinUpRZwN?= =?us-ascii?Q?srN8AWOoha07NJZoSkXaTs5X5m1yXYdXiMuYRjW5un04RbV90PYGEVJW/9fH?= =?us-ascii?Q?dRTDwV6WSvjHmGzLKliJTmZziIKjYXBULHqEv73LGwm9nV3TPyWxvuIwvKjf?= =?us-ascii?Q?lBpMpMf4PRJuIs91U+6oecGld6PSP72AJudzYmfDNxAJQbjLd3goOz7i1G4V?= =?us-ascii?Q?Fen1DoLxA8zdZxEgQog5mj9ioycLuwmnJMz4gl20IE1XkTG9x3W/azjMy9M1?= =?us-ascii?Q?QBvj65Yw/76YrabCTOkynbFXbjeNh1lQlvtYtmUmETaSnc3PVU/H0rq00+zq?= =?us-ascii?Q?tLgOXlmINjmmObqROsLtM47u42gxJztvKLlYNOs21OqdiX/hiY2975mb7LrX?= =?us-ascii?Q?wNR33N/JXDT0maCzQ0p9BFs2WlZuwg5ceFrx7jspb2b7bpwp0WfHQAaZ51Ri?= =?us-ascii?Q?yyJSsSLMQCrvzWsLeyJIA3YHTL0ZtIEqJSTs0SvyGRpP219AngYHyOB9J/uY?= =?us-ascii?Q?qhMkjvMKhtkGfMYl/NeOeOcumWT2cLa2guSThvHJWSYTDCFFOHpqi9tI8wH9?= =?us-ascii?Q?NBM9rdYbNv9RzAf5QkKXpGZloxFB0OQoow4N61SadgRaFowz6jotSL+9IeDE?= =?us-ascii?Q?Bo0SgyzWEbEuiW1wH06Cer7XGic+v1rZAiwdRsmaUYDDtMc24gyUqNgguMaz?= =?us-ascii?Q?Z6MwU3xzQzxrdVmVBwYpXfh+1inlxcAC64VscvcJsimKRMQKj7fyKDnvg7lG?= =?us-ascii?Q?N0wUD7c6Wj7TJ+P6xluLj48lUu9RO08w1Qn0h4JJ8070u8JsG4st8b4TOnW2?= =?us-ascii?Q?RtFlqrwD1KTJGVImFyKLDYQJgeyNvIiss5RaWWDb3MAzbB7I6R9PyC/z1g0O?= =?us-ascii?Q?ArKsC0kA3GeoLmOzeDTHI/P93XDojCAxuNdcWWHABoQbsbJHZ4+utXYOAo+z?= =?us-ascii?Q?H6dYareLbY7CsldiaCS9CfKDKUjrIKEBFzaim63i0i8WXmSXTGszdCnTF6CK?= =?us-ascii?Q?YuObHj1U5D74mp3hl/2LECLQ79gt7QQcKDd56fnfZwp7X5cyJN8SD7lRpSg1?= =?us-ascii?Q?w09PojrZlOjWDsqbLb076D891l9rGqyK5s82+3CqExohxJeS9Q=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:51:08.9252 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7becad32-3c21-454a-ce6b-08dcf54fe5fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4276 Content-Type: text/plain; charset="utf-8" Add a viommu_cache test function to cover vIOMMU invalidations using the updated IOMMU_HWPT_INVALIDATE ioctl, which now allows passing in a vIOMMU via its hwpt_id field. Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- tools/testing/selftests/iommu/iommufd_utils.h | 32 ++++ tools/testing/selftests/iommu/iommufd.c | 173 ++++++++++++++++++ 2 files changed, 205 insertions(+) diff --git a/tools/testing/selftests/iommu/iommufd_utils.h b/tools/testing/= selftests/iommu/iommufd_utils.h index 3ae6cb5eed7d..aa458c80ad30 100644 --- a/tools/testing/selftests/iommu/iommufd_utils.h +++ b/tools/testing/selftests/iommu/iommufd_utils.h @@ -289,6 +289,38 @@ static int _test_cmd_hwpt_invalidate(int fd, __u32 hwp= t_id, void *reqs, data_type, lreq, nreqs)); \ }) =20 +static int _test_cmd_viommu_invalidate(int fd, __u32 viommu_id, void *reqs, + uint32_t data_type, uint32_t lreq, + uint32_t *nreqs) +{ + struct iommu_hwpt_invalidate cmd =3D { + .size =3D sizeof(cmd), + .hwpt_id =3D viommu_id, + .data_type =3D data_type, + .data_uptr =3D (uint64_t)reqs, + .entry_len =3D lreq, + .entry_num =3D *nreqs, + }; + int rc =3D ioctl(fd, IOMMU_HWPT_INVALIDATE, &cmd); + *nreqs =3D cmd.entry_num; + return rc; +} + +#define test_cmd_viommu_invalidate(viommu, reqs, lreq, nreqs) = \ + ({ \ + ASSERT_EQ(0, \ + _test_cmd_viommu_invalidate(self->fd, viommu, reqs, \ + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, \ + lreq, nreqs)); \ + }) +#define test_err_viommu_invalidate(_errno, viommu_id, reqs, data_type, lre= q, \ + nreqs) \ + ({ \ + EXPECT_ERRNO(_errno, _test_cmd_viommu_invalidate( \ + self->fd, viommu_id, reqs, \ + data_type, lreq, nreqs)); \ + }) + static int _test_cmd_access_replace_ioas(int fd, __u32 access_id, unsigned int ioas_id) { diff --git a/tools/testing/selftests/iommu/iommufd.c b/tools/testing/selfte= sts/iommu/iommufd.c index ff0181e5db48..9a7d4b9c44f6 100644 --- a/tools/testing/selftests/iommu/iommufd.c +++ b/tools/testing/selftests/iommu/iommufd.c @@ -2498,4 +2498,177 @@ TEST_F(iommufd_viommu, vdevice_alloc) } } =20 +TEST_F(iommufd_viommu, vdevice_cache) +{ + struct iommu_viommu_invalidate_selftest inv_reqs[2] =3D {}; + uint32_t viommu_id =3D self->viommu_id; + uint32_t dev_id =3D self->device_id; + uint32_t vdev_id =3D 0; + uint32_t num_inv; + + if (dev_id) { + test_cmd_vdevice_alloc(viommu_id, dev_id, 0x99, &vdev_id); + + test_cmd_dev_check_cache_all(dev_id, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Check data_type by passing zero-length array */ + num_inv =3D 0; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: Invalid data_type */ + num_inv =3D 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST_INVALID, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: structure size sanity */ + num_inv =3D 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs) + 1, &num_inv); + assert(!num_inv); + + num_inv =3D 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + 1, &num_inv); + assert(!num_inv); + + /* Negative test: invalid flag is passed */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0xffffffff; + inv_reqs[0].vdev_id =3D 0x99; + test_err_viommu_invalidate(EOPNOTSUPP, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid data_uptr when array is not empty */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + test_err_viommu_invalidate(EINVAL, viommu_id, NULL, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid entry_len when array is not empty */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + 0, &num_inv); + assert(!num_inv); + + /* Negative test: invalid cache_id */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D MOCK_DEV_CACHE_ID_MAX + 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* Negative test: invalid vdev_id */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x9; + inv_reqs[0].cache_id =3D 0; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(!num_inv); + + /* + * Invalidate the 1st cache entry but fail the 2nd request + * due to invalid flags configuration in the 2nd request. + */ + num_inv =3D 2; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D 0; + inv_reqs[1].flags =3D 0xffffffff; + inv_reqs[1].vdev_id =3D 0x99; + inv_reqs[1].cache_id =3D 1; + test_err_viommu_invalidate(EOPNOTSUPP, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* + * Invalidate the 1st cache entry but fail the 2nd request + * due to invalid cache_id configuration in the 2nd request. + */ + num_inv =3D 2; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D 0; + inv_reqs[1].flags =3D 0; + inv_reqs[1].vdev_id =3D 0x99; + inv_reqs[1].cache_id =3D MOCK_DEV_CACHE_ID_MAX + 1; + test_err_viommu_invalidate(EINVAL, viommu_id, inv_reqs, + IOMMU_VIOMMU_INVALIDATE_DATA_SELFTEST, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Invalidate the 2nd cache entry and verify */ + num_inv =3D 1; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D 1; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 1); + test_cmd_dev_check_cache(dev_id, 0, 0); + test_cmd_dev_check_cache(dev_id, 1, 0); + test_cmd_dev_check_cache(dev_id, 2, + IOMMU_TEST_DEV_CACHE_DEFAULT); + test_cmd_dev_check_cache(dev_id, 3, + IOMMU_TEST_DEV_CACHE_DEFAULT); + + /* Invalidate the 3rd and 4th cache entries and verify */ + num_inv =3D 2; + inv_reqs[0].flags =3D 0; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].cache_id =3D 2; + inv_reqs[1].flags =3D 0; + inv_reqs[1].vdev_id =3D 0x99; + inv_reqs[1].cache_id =3D 3; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 2); + test_cmd_dev_check_cache_all(dev_id, 0); + + /* Invalidate all cache entries for nested_dev_id[1] and verify */ + num_inv =3D 1; + inv_reqs[0].vdev_id =3D 0x99; + inv_reqs[0].flags =3D IOMMU_TEST_INVALIDATE_FLAG_ALL; + test_cmd_viommu_invalidate(viommu_id, inv_reqs, + sizeof(*inv_reqs), &num_inv); + assert(num_inv =3D=3D 1); + test_cmd_dev_check_cache_all(dev_id, 0); + test_ioctl_destroy(vdev_id); + } +} + TEST_HARNESS_MAIN --=20 2.43.0