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Mon, 15 Dec 2025 13:42:33 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v8 5/5] PCI: Suspend iommu function prior to resetting a device Date: Mon, 15 Dec 2025 13:42:20 -0800 Message-ID: <348c50ab6e95b5ec6d48ee3fa05d529a784a34c3.1765834788.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7B:EE_|SA0PR12MB4479:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c7259a3-290b-4544-5679-08de3c22e700 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|7416014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?rtfvOZ5Hmv/useHYXgvnhtwbjGHAEAsVXAzBK5tnhSRTHMB0sPaWl+szqacj?= =?us-ascii?Q?SOCc0dHqj2Pc706g2EecdZ5jcwvJs2+o4L1Ws+y+AQ+UIF3iUKejjMbAZ1dK?= =?us-ascii?Q?h/+cND66zUjINKJF4E6kJKKg651W5IMPLQPvs1iZbjK7oYZhmA5MQBRnYmTz?= =?us-ascii?Q?7/2ZbF8FE1oj/v2NvTg5W6/xd5+o2T9zOHEtJmhG6/0KJfg+S/ZO07QU4k0W?= =?us-ascii?Q?OA1zzQIGSHOcb6WimhSqrLJ6Vx6Wz2/X/0o/1Llf1ROdOYqTHS9J1JFPwDTa?= =?us-ascii?Q?SV8k5WiQnzQ7M4/c2eo4BOFUQTRCrsi74PsE1L6rJBiMmNH5k3+qNJPKpNJr?= =?us-ascii?Q?hyKQMiJFBNnsWNsRtK6SWaZ5Oa30R2FvedeTlt0fD211VRxtXeXc1PhwO6KN?= =?us-ascii?Q?L0q7Kd08EpymJBQ0UCyl0KxkcTfZkzY+cs8l7nOBVdqRvI6HnvZWZ+n8wkWG?= =?us-ascii?Q?LUegXyq2544MvCMc/O2tRh18u/Tkmfkg6RBiqLdA03TS5ssnSP3Z2gvJ1aub?= =?us-ascii?Q?Wpjc87X8TNoHkb/UXoZUiUaBzN9ZYPmlNAHLLp8nPwPF0PGY8Z9UicWNbB7M?= =?us-ascii?Q?nzocMPtqhsmJtlRpWYe57vzJhij1LQel/n5A3o5Go03s7GZnNvNwyqm+kpoJ?= =?us-ascii?Q?rsZXaaTBbgTQWw9xIxQ7hg33mksgyNn4YW0iv87fNhNjmvD2q3XddWL/Fsd9?= =?us-ascii?Q?/pF2bba048jW/h+rDG3gf7ViseTQLnw/AsRjDZKj+8pVDiV7vLtAOmxDCk21?= =?us-ascii?Q?M1t4DFa7kUyq0wM+0AI9uis9TwcYcj8Kyb2fGIS4WbzwkarqJVWKOubRzYwa?= =?us-ascii?Q?2dzJ6qYIXL5oW7e2lF8nrZ8Ysy6X4m9TwOkqF1a7/yXqYynfqjhGMIZLBP5/?= =?us-ascii?Q?F2OQ847QTy3tmw5PiKeIMb+oteen1g5uPuzy9jhQka3+H201YPCtgZ46SroO?= =?us-ascii?Q?KpyALHSUpo2sdtgcZnk6BF7hoDG4g8dk7tuVdAwdNJiKV9ff+qJFfZlrbdB2?= =?us-ascii?Q?DOhOhVeC1iCTRbUdVkMO3I/CFaXbf53EFC+WPdnuubB+4VzZq7FrD6M6YaX+?= =?us-ascii?Q?frU5Eeale1d00O8TgtxA9H9skTggTXus/a5R8EHXTbFrxlbbW+m2+/VZ61DA?= =?us-ascii?Q?obf9qQwmhcmj1N8ihVXR5HhhjrgPC8iChmCOco118nRXi/AeeaVd6ZQBtDBj?= =?us-ascii?Q?g+UM83sP8VI30lbPZkem7F3HYUFGiKpRQF3NRHnMZtg43cV2V8NIWAM5kB5B?= =?us-ascii?Q?Gd/cKBGPCd0QigV7ZArIfNwFGtUCuGq4Z/KLb66LOQ4EGocixAqk0mWxq/s/?= =?us-ascii?Q?HDLmYtU4Vm6JQMEoaP7UWrhmWyTcadOFu1TrC0Ph1w8J/5HA5v1pZdrIxzA3?= =?us-ascii?Q?eqQmY+iJ5dBit/4+1WJgnkq2BKYiDwzSTXI2Aml7o+vw7+x29Ry33SC8UHt2?= =?us-ascii?Q?THL7PGYYK3MeTjMehEI+otzz6/VBoYmLw0jXrJbqwfBXz/y+Owa64Gw0W5TZ?= =?us-ascii?Q?6zkOebvf1VocdTuZv873CvXkOp3lUn7FhTWIWaDm1jFNSDErUqUdgz27zkfn?= =?us-ascii?Q?6H1yDV6cCR45R7EZxx4=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(7416014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Dec 2025 21:42:53.3897 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c7259a3-290b-4544-5679-08de3c22e700 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4479 Content-Type: text/plain; charset="utf-8" PCIe permits a device to ignore ATS invalidation TLPs while processing a reset. This creates a problem visible to the OS where an ATS invalidation command will time out: e.g. an SVA domain will have no coordination with a reset event and can racily issue ATS invalidations to a resetting device. The PCIe r6.0, sec 10.3.1 IMPLEMENTATION NOTE recommends SW to disable and block ATS before initiating a Function Level Reset. It also mentions that other reset methods could have the same vulnerability as well. The IOMMU subsystem provides pci_dev_reset_iommu_prepare/done() callback helpers for this matter. Use them in all the existing reset functions. This will attach the device to its iommu_group->blocking_domain during the device reset, so as to allow IOMMU driver to: - invoke pci_disable_ats() and pci_enable_ats(), if necessary - wait for all ATS invalidations to complete - stop issuing new ATS invalidations - fence any incoming ATS queries Reviewed-by: Kevin Tian Reviewed-by: Jason Gunthorpe Acked-by: Bjorn Helgaas Tested-by: Dheeraj Kumar Srivastava Signed-off-by: Nicolin Chen --- drivers/pci/pci-acpi.c | 13 +++++++-- drivers/pci/pci.c | 65 +++++++++++++++++++++++++++++++++++++----- drivers/pci/quirks.c | 19 +++++++++++- 3 files changed, 87 insertions(+), 10 deletions(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 9369377725fa..651d9b5561ff 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include #include #include @@ -971,6 +972,7 @@ void pci_set_acpi_fwnode(struct pci_dev *dev) int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) { acpi_handle handle =3D ACPI_HANDLE(&dev->dev); + int ret; =20 if (!handle || !acpi_has_method(handle, "_RST")) return -ENOTTY; @@ -978,12 +980,19 @@ int pci_dev_acpi_reset(struct pci_dev *dev, bool prob= e) if (probe) return 0; =20 + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) { pci_warn(dev, "ACPI _RST failed\n"); - return -ENOTTY; + ret =3D -ENOTTY; } =20 - return 0; + pci_dev_reset_iommu_done(dev); + return ret; } =20 bool acpi_pci_power_manageable(struct pci_dev *dev) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 13dbb405dc31..a0ba42ae7ee0 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -4330,13 +4332,22 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction); */ int pcie_flr(struct pci_dev *dev) { + int ret; + if (!pci_wait_for_pending_transaction(dev)) pci_err(dev, "timed out waiting for pending transaction; performing func= tion level reset anyway\n"); =20 + /* Have to call it after waiting for pending DMA transaction */ + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within @@ -4345,7 +4356,10 @@ int pcie_flr(struct pci_dev *dev) */ msleep(100); =20 - return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS); +done: + pci_dev_reset_iommu_done(dev); + return ret; } EXPORT_SYMBOL_GPL(pcie_flr); =20 @@ -4373,6 +4387,7 @@ EXPORT_SYMBOL_GPL(pcie_reset_flr); =20 static int pci_af_flr(struct pci_dev *dev, bool probe) { + int ret; int pos; u8 cap; =20 @@ -4399,10 +4414,17 @@ static int pci_af_flr(struct pci_dev *dev, bool pro= be) PCI_AF_STATUS_TP << 8)) pci_err(dev, "timed out waiting for pending transaction; performing AF f= unction level reset anyway\n"); =20 + /* Have to call it after waiting for pending DMA transaction */ + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR); =20 if (dev->imm_ready) - return 0; + goto done; =20 /* * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006, @@ -4412,7 +4434,10 @@ static int pci_af_flr(struct pci_dev *dev, bool prob= e) */ msleep(100); =20 - return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS); +done: + pci_dev_reset_iommu_done(dev); + return ret; } =20 /** @@ -4433,6 +4458,7 @@ static int pci_af_flr(struct pci_dev *dev, bool probe) static int pci_pm_reset(struct pci_dev *dev, bool probe) { u16 csr; + int ret; =20 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) return -ENOTTY; @@ -4447,6 +4473,12 @@ static int pci_pm_reset(struct pci_dev *dev, bool pr= obe) if (dev->current_state !=3D PCI_D0) return -EINVAL; =20 + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + csr &=3D ~PCI_PM_CTRL_STATE_MASK; csr |=3D PCI_D3hot; pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); @@ -4457,7 +4489,9 @@ static int pci_pm_reset(struct pci_dev *dev, bool pro= be) pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); pci_dev_d3_sleep(dev); =20 - return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + ret =3D pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); + pci_dev_reset_iommu_done(dev); + return ret; } =20 /** @@ -4885,10 +4919,20 @@ static int pci_reset_bus_function(struct pci_dev *d= ev, bool probe) return -ENOTTY; } =20 + rc =3D pci_dev_reset_iommu_prepare(dev); + if (rc) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", rc); + return rc; + } + rc =3D pci_dev_reset_slot_function(dev, probe); if (rc !=3D -ENOTTY) - return rc; - return pci_parent_bus_reset(dev, probe); + goto done; + + rc =3D pci_parent_bus_reset(dev, probe); +done: + pci_dev_reset_iommu_done(dev); + return rc; } =20 static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) @@ -4912,6 +4956,12 @@ static int cxl_reset_bus_function(struct pci_dev *de= v, bool probe) if (rc) return -ENOTTY; =20 + rc =3D pci_dev_reset_iommu_prepare(dev); + if (rc) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", rc); + return rc; + } + if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR) { val =3D reg; } else { @@ -4926,6 +4976,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev= , bool probe) pci_write_config_word(bridge, dvsec + PCI_DVSEC_CXL_PORT_CTL, reg); =20 + pci_dev_reset_iommu_done(dev); return rc; } =20 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index b9c252aa6fe0..c6b999045c70 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -21,6 +21,7 @@ #include #include /* isa_dma_bridge_buggy */ #include +#include #include #include #include @@ -4228,6 +4229,22 @@ static const struct pci_dev_reset_methods pci_dev_re= set_methods[] =3D { { 0 } }; =20 +static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, + const struct pci_dev_reset_methods *i) +{ + int ret; + + ret =3D pci_dev_reset_iommu_prepare(dev); + if (ret) { + pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); + return ret; + } + + ret =3D i->reset(dev, probe); + pci_dev_reset_iommu_done(dev); + return ret; +} + /* * These device-specific reset methods are here rather than in a driver * because when a host assigns a device to a guest VM, the host may need @@ -4242,7 +4259,7 @@ int pci_dev_specific_reset(struct pci_dev *dev, bool = probe) i->vendor =3D=3D (u16)PCI_ANY_ID) && (i->device =3D=3D dev->device || i->device =3D=3D (u16)PCI_ANY_ID)) - return i->reset(dev, probe); + return __pci_dev_specific_reset(dev, probe, i); } =20 return -ENOTTY; --=20 2.43.0