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Mon, 30 Jun 2025 10:00:36 -0400 From: Marcelo Schmitt To: , , , CC: , , , , , , , , , , , , , Subject: [PATCH v7 08/12] iio: adc: ad4170-4: Add clock provider support Date: Mon, 30 Jun 2025 11:00:32 -0300 Message-ID: <3373d02579fb3f2c45f845984b2cf9b979221fb8.1751289747.git.marcelo.schmitt@analog.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjMwMDExNSBTYWx0ZWRfXy45lSMYlr7G2 cIDlW8SujRYjy+3yHZc49TjQPW/6Fpt+1wo2d6Tv2boFJ43GpdsgCfwW4Zb+uuR+8HXY8GObBeP uFRMp/pVJRR5OddNZl96AuPjeE9A6SGftqes6UMuo/tbf0Tpfsa39IrV8iZvABWQxXQTLM/OzdZ wbbqRbIVXEqEyYhS0PjeK4BsfvZ8hdTiMlu85gCgFOs3AO5+lP/xlyyeAAnNclrf7xGTM6d3pKE IQL9XM1m2wtbEZxm0enZVX0qM6DuAJoQUpdN+tSRomu/88pyuvtPBc1K+tMSfjyhGcmYWjNOLdR AZ9qVos85R2jpEpbEN3aZNtGLFwzKn4GLfrGx8B7RPgJZ06s+qqCbEZnKdmLeLCDhPAjW49mdFq XtqIYf+X2oiMsgw8C7KzwkFnyaKrqx7mKTA7AgxiEbVQiibwKTgFp0aooiXXXBuBjmu8FKvp X-Proofpoint-GUID: osX5q-y1O1ZURLfIBEwXZEhq117u8_Hu X-Proofpoint-ORIG-GUID: osX5q-y1O1ZURLfIBEwXZEhq117u8_Hu X-Authority-Analysis: v=2.4 cv=U8+SDfru c=1 sm=1 tr=0 ts=68629895 cx=c_pps a=PpDZqlmH/M8setHirZLBMw==:117 a=PpDZqlmH/M8setHirZLBMw==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=gAnH3GRIAAAA:8 a=FbnkXhljGIpD8s1dgEMA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-30_03,2025-06-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 mlxscore=0 bulkscore=0 suspectscore=0 adultscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506300115 The AD4170-4 chip can use an externally supplied clock at the XTAL2 pin, or an external crystal connected to the XTAL1 and XTAL2 pins. Alternatively, the AD4170-4 can provide its 16 MHz internal clock at the XTAL2 pin. In addition, the chip has a programmable clock divider that allows dividing the external or internal clock frequency, however, control for that is not provided in this patch. Extend the AD4170-4 driver so it effectively uses the provided external clock, if any, or supplies its own clock as a clock provider. Reviewed-by: Nuno S=C3=A1 Signed-off-by: Marcelo Schmitt --- No changes since v6. drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad4170-4.c | 147 ++++++++++++++++++++++++++++++++++++- 2 files changed, 147 insertions(+), 1 deletion(-) diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 538929b3df6e..36e506e8d8f1 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -91,6 +91,7 @@ config AD4170_4 select REGMAP_SPI select IIO_BUFFER select IIO_TRIGGERED_BUFFER + depends on COMMON_CLK help Say yes here to build support for Analog Devices AD4170-4 SPI analog to digital converters (ADC). diff --git a/drivers/iio/adc/ad4170-4.c b/drivers/iio/adc/ad4170-4.c index 9202a8dfcc16..bf261d4ef67d 100644 --- a/drivers/iio/adc/ad4170-4.c +++ b/drivers/iio/adc/ad4170-4.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -55,6 +57,7 @@ #define AD4170_CONFIG_A_REG 0x00 #define AD4170_DATA_24B_REG 0x1E #define AD4170_PIN_MUXING_REG 0x69 +#define AD4170_CLOCK_CTRL_REG 0x6B #define AD4170_ADC_CTRL_REG 0x71 #define AD4170_CHAN_EN_REG 0x79 #define AD4170_CHAN_SETUP_REG(x) (0x81 + 4 * (x)) @@ -75,6 +78,9 @@ /* AD4170_PIN_MUXING_REG */ #define AD4170_PIN_MUXING_DIG_AUX1_CTRL_MSK GENMASK(5, 4) =20 +/* AD4170_CLOCK_CTRL_REG */ +#define AD4170_CLOCK_CTRL_CLOCKSEL_MSK GENMASK(1, 0) + /* AD4170_ADC_CTRL_REG */ #define AD4170_ADC_CTRL_MULTI_DATA_REG_SEL_MSK BIT(7) #define AD4170_ADC_CTRL_CONT_READ_MSK GENMASK(5, 4) @@ -102,6 +108,12 @@ =20 /* AD4170 register constants */ =20 +/* AD4170_CLOCK_CTRL_REG constants */ +#define AD4170_CLOCK_CTRL_CLOCKSEL_INT 0x0 +#define AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT 0x1 +#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT 0x2 +#define AD4170_CLOCK_CTRL_CLOCKSEL_EXT_XTAL 0x3 + /* AD4170_CHAN_MAP_REG constants */ #define AD4170_CHAN_MAP_AIN(x) (x) #define AD4170_CHAN_MAP_TEMP_SENSOR 17 @@ -149,6 +161,8 @@ =20 /* Internal and external clock properties */ #define AD4170_INT_CLOCK_16MHZ (16 * HZ_PER_MHZ) +#define AD4170_EXT_CLOCK_MHZ_MIN (1 * HZ_PER_MHZ) +#define AD4170_EXT_CLOCK_MHZ_MAX (17 * HZ_PER_MHZ) =20 #define AD4170_NUM_PGA_OPTIONS 10 =20 @@ -166,6 +180,7 @@ static const unsigned int ad4170_reg_size[] =3D { [AD4170_CONFIG_A_REG] =3D 1, [AD4170_DATA_24B_REG] =3D 3, [AD4170_PIN_MUXING_REG] =3D 2, + [AD4170_CLOCK_CTRL_REG] =3D 2, [AD4170_ADC_CTRL_REG] =3D 2, [AD4170_CHAN_EN_REG] =3D 2, /* @@ -238,6 +253,10 @@ enum ad4170_regulator { AD4170_MAX_SUP, }; =20 +static const char *const ad4170_clk_sel[] =3D { + "ext-clk", "xtal", +}; + enum ad4170_int_pin_sel { AD4170_INT_PIN_SDO, AD4170_INT_PIN_DIG_AUX1, @@ -340,6 +359,8 @@ struct ad4170_state { struct completion completion; unsigned int pins_fn[AD4170_NUM_ANALOG_PINS]; u32 int_pin_sel; + struct clk_hw int_clk_hw; + unsigned int clock_ctrl; /* * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines. @@ -1623,13 +1644,137 @@ static int ad4170_parse_channels(struct iio_dev *i= ndio_dev) return 0; } =20 +static struct ad4170_state *clk_hw_to_ad4170(struct clk_hw *hw) +{ + return container_of(hw, struct ad4170_state, int_clk_hw); +} + +static unsigned long ad4170_sel_clk(struct ad4170_state *st, + unsigned int clk_sel) +{ + st->clock_ctrl &=3D ~AD4170_CLOCK_CTRL_CLOCKSEL_MSK; + st->clock_ctrl |=3D FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, clk_sel); + return regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl); +} + +static unsigned long ad4170_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return AD4170_INT_CLOCK_16MHZ; +} + +static int ad4170_clk_output_is_enabled(struct clk_hw *hw) +{ + struct ad4170_state *st =3D clk_hw_to_ad4170(hw); + u32 clk_sel; + + clk_sel =3D FIELD_GET(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, st->clock_ctrl); + return clk_sel =3D=3D AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT; +} + +static int ad4170_clk_output_prepare(struct clk_hw *hw) +{ + struct ad4170_state *st =3D clk_hw_to_ad4170(hw); + + return ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT); +} + +static void ad4170_clk_output_unprepare(struct clk_hw *hw) +{ + struct ad4170_state *st =3D clk_hw_to_ad4170(hw); + + ad4170_sel_clk(st, AD4170_CLOCK_CTRL_CLOCKSEL_INT); +} + +static const struct clk_ops ad4170_int_clk_ops =3D { + .recalc_rate =3D ad4170_clk_recalc_rate, + .is_enabled =3D ad4170_clk_output_is_enabled, + .prepare =3D ad4170_clk_output_prepare, + .unprepare =3D ad4170_clk_output_unprepare, +}; + +static int ad4170_register_clk_provider(struct iio_dev *indio_dev) +{ + struct ad4170_state *st =3D iio_priv(indio_dev); + struct device *dev =3D indio_dev->dev.parent; + struct clk_init_data init =3D {}; + int ret; + + if (device_property_read_string(dev, "clock-output-names", &init.name)) { + init.name =3D devm_kasprintf(dev, GFP_KERNEL, "%pfw", + dev_fwnode(dev)); + if (!init.name) + return -ENOMEM; + } + + init.ops =3D &ad4170_int_clk_ops; + + st->int_clk_hw.init =3D &init; + ret =3D devm_clk_hw_register(dev, &st->int_clk_hw); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &st->int_clk_hw); +} + +static int ad4170_clock_select(struct iio_dev *indio_dev) +{ + struct ad4170_state *st =3D iio_priv(indio_dev); + struct device *dev =3D &st->spi->dev; + struct clk *ext_clk; + int ret; + + ext_clk =3D devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(ext_clk)) + return dev_err_probe(dev, PTR_ERR(ext_clk), + "Failed to get external clock\n"); + + if (!ext_clk) { + /* Use internal clock reference */ + st->mclk_hz =3D AD4170_INT_CLOCK_16MHZ; + st->clock_ctrl |=3D FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, + AD4170_CLOCK_CTRL_CLOCKSEL_INT_OUT); + + if (!device_property_present(&st->spi->dev, "#clock-cells")) + return 0; + + return ad4170_register_clk_provider(indio_dev); + } + + /* Read optional clock-names prop to specify the external clock type */ + ret =3D device_property_match_property_string(dev, "clock-names", + ad4170_clk_sel, + ARRAY_SIZE(ad4170_clk_sel)); + + ret =3D ret < 0 ? 0 : ret; /* Default to external clock if no clock-names= */ + st->clock_ctrl |=3D FIELD_PREP(AD4170_CLOCK_CTRL_CLOCKSEL_MSK, + AD4170_CLOCK_CTRL_CLOCKSEL_EXT + ret); + + st->mclk_hz =3D clk_get_rate(ext_clk); + if (st->mclk_hz < AD4170_EXT_CLOCK_MHZ_MIN || + st->mclk_hz > AD4170_EXT_CLOCK_MHZ_MAX) { + return dev_err_probe(dev, -EINVAL, + "Invalid external clock frequency %u\n", + st->mclk_hz); + } + + return 0; +} + static int ad4170_parse_firmware(struct iio_dev *indio_dev) { struct ad4170_state *st =3D iio_priv(indio_dev); struct device *dev =3D &st->spi->dev; int reg_data, ret; =20 - st->mclk_hz =3D AD4170_INT_CLOCK_16MHZ; + ret =3D ad4170_clock_select(indio_dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to setup device clock\n"); + + ret =3D regmap_write(st->regmap, AD4170_CLOCK_CTRL_REG, st->clock_ctrl); + if (ret) + return ret; =20 /* On power on, device defaults to using SDO pin for data ready signal */ st->int_pin_sel =3D AD4170_INT_PIN_SDO; --=20 2.47.2