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Fri, 27 May 2022 18:40:59 +0000 From: To: CC: , , , , , Subject: Reset controller within a clock driver Thread-Topic: Reset controller within a clock driver Thread-Index: AQHYcflPoksJXIVaQkOgoJTQWMRNig== Date: Fri, 27 May 2022 18:40:59 +0000 Message-ID: <31b7293f-662d-4a94-1717-9c76d7f33840@microchip.com> Accept-Language: en-IE, en-US Content-Language: en-IE X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microchip.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4b160437-77ce-4e02-6db5-08da40107186 x-ms-traffictypediagnostic: DM4PR11MB6213:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: LCXhkzW+MUuzU2Nq5AXvL2I20rTtTe35UnnOrWfVqTY6M8W7PPChV8VDkznC6teVD0bMV5ZlS4kTfqETDr4l/0gL2cYCMEg1Hq00yMuwr4tAAbfZh+tF+VVaO8rhZc9Gnlu2iFFBqDqiP4GlCANT7Z3pK38c80OgOBiVmRx7YVJ+KFgrxC2oNFcFja+bfhef2X+3uuciOPk9Txu9+s+OjH3TIHj+ufVim6gLuGLdBhRikcn/3iroH17Z8gyXK3k3EWnYinYp06D8gagbfPk9h45mkiVtWNsjujCUz+FkIa6lczOPN6lN1Nmmzk4BMnKbkvKSs1IsTCc9rVcAWjVzG72Wyi8GFHBz1WUYfD3cCj4tKJEGwZKZ7Q/7hrQlD9H8fme4jtxTFvAFcSoR4I2Khu8YPTcEmcrRKsMnOkBLCmfPGLrQPr8LSGLyRxl5DHwigQ7DAeDaFx1jlcnLGaRaY0AzpwiIpzQaTZbvQgVBvlxjKj8zVqc+GY0FE8Ys7Y9PzH6pOEoNILHHL5lBbh7VT5o+EC7o3iMpC6NNu5NN9TtRn/9CQHCO0P379tA0IFBo3b8B+755uqtUy0ngPTM5kVB/jXR4af6Y66pHvAWQTVfDUkUxRdjxSfdHqvIoOnR/VKl4KMBfpDWt/c0LY9/Pt7QI3kcYY5uvsXxS4H+ntF+QtZJ6gvd19TSI5z8PzNvrcVEhryrizj2NeVcdimONHHholb5NBWMkvVSCDjVr24g6U+8XPM3uT9hLB2nU8l+bSVCQSYyo1cgh0I8Oq7+kDaXFk7WjPi4pov1ObeG/M/ZCeCMnb/2VZecOuolIjGarN4b/GETAz0IYrsA0hD9j7m41C7pAwTzCuopjKZhWmIuF6RyZ6VgjgyIe4/5Uf9vA6BxpJFGHNJzPp4wX7jxOyA== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:CO1PR11MB5154.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230001)(366004)(76116006)(64756008)(54906003)(38070700005)(6916009)(2906002)(66556008)(66446008)(8676002)(186003)(31696002)(316002)(66476007)(71200400001)(83380400001)(36756003)(5660300002)(31686004)(86362001)(66946007)(2616005)(6486002)(6506007)(26005)(6512007)(91956017)(966005)(38100700002)(4326008)(122000001)(508600001)(8936002)(45980500001)(43740500002);DIR:OUT;SFP:1101; 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charset="utf-8" Content-ID: Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO1PR11MB5154.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4b160437-77ce-4e02-6db5-08da40107186 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 May 2022 18:40:59.4323 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hUKzlLyytZ5q8MilJ3rDTFlVEUyPjIzSysW6n62qGoLh+RnTaGZUmlVszkf2NGhkyuFY4e71NGGCKicxXHadpi5Som9/CbfkmT7tf7O6VAE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR11MB6213 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Stephen, After I sent the fix for the broken resets in clk/microchip/clk-mpfs.c, [0] I started looking at making a proper reset controller driver a la clk/renesas/{renesas-cpg-mssr,rzgl2l-cpg}.c where the reset controller is part of the clock driver file. I did it that way b/c the reset controller is just a single reg, surrounded by registers used by clocks. It's roughly a +130,-10 line change to the existing driver. A /very/ rough version that will not apply without other cleanup is appended for context. Before I got around to testing properly and cleaning it up for submission, I saw a mail you had sent and wondered if I'd gone for the wrong approach [1]. Should I instead have my clock driver create a device for the reset controller to bind to, or is that overkill for a single register & Serge's situation is different b/c he'd created a file purely for a reset controller? Thanks, Conor. 0 - https://lore.kernel.org/linux-clk/20220411072340.740981-1-conor.dooley@= microchip.com/ 1 - https://lore.kernel.org/linux-clk/20220517073729.2FAE2C385B8@smtp.kerne= l.org/ diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-m= pfs.c index ce3a48472fba..d9d1a4d9f131 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include =20 @@ -29,7 +30,13 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u =20 +#define MPFS_PERIPH_OFFSET 3u + struct mpfs_clock_data { + struct device *dev; +#ifdef CONFIG_RESET_CONTROLLER + struct reset_controller_dev rcdev; +#endif void __iomem *base; void __iomem *msspll_base; struct clk_hw_onecell_data hw_data; @@ -344,10 +351,6 @@ static int mpfs_periph_clk_enable(struct clk_hw *hw) =20 spin_lock_irqsave(&mpfs_clk_lock, flags); =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - val =3D reg & ~(1u << periph->shift); - writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR); - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); val =3D reg | (1u << periph->shift); writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR); @@ -381,12 +384,9 @@ static int mpfs_periph_clk_is_enabled(struct clk_hw *h= w) void __iomem *base_addr =3D periph_hw->base; u32 reg; =20 - reg =3D readl_relaxed(base_addr + REG_SUBBLK_RESET_CR); - if ((reg & (1u << periph->shift)) =3D=3D 0u) { - reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); - if (reg & (1u << periph->shift)) - return 1; - } + reg =3D readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR); + if (reg & (1u << periph->shift)) + return 1; =20 return 0; } @@ -472,6 +472,118 @@ static int mpfs_clk_register_periphs(struct device *d= ev, struct mpfs_periph_hw_c return 0; } =20 +/* + * Peripheral clock resets + * + * CLK_RESERVED does not map to a clock, but it does map to a reset line, = so it + * has to be accounted for here. + * + */ + +#ifdef CONFIG_RESET_CONTROLLER + +#define rcdev_to_clock_data(x) container_of((x), struct mpfs_clock_data, r= cdev) + +// static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long= id) +// {=20 +// struct mpfs_clock_data *clk_data =3D rcdev_to_clock_data(rcdev); +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// +// return 0; +// } + +static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long i= d) +{ + struct mpfs_clock_data *clk_data =3D rcdev_to_clock_data(rcdev); + u32 reg, val; + + reg =3D readl_relaxed(clk_data->base + REG_SUBBLK_RESET_CR); + val =3D reg | (1u << id); + writel_relaxed(val, clk_data->base + REG_SUBBLK_RESET_CR); + + dev_dbg(clk_data->dev, "deassert reset: %02lu\n", id); + return 0; +} + +static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long= id) +{ + struct mpfs_clock_data *clk_data =3D rcdev_to_clock_data(rcdev); + u32 reg, val; + + reg =3D readl_relaxed(clk_data->base + REG_SUBBLK_RESET_CR); + val =3D reg & ~(1u << id); + writel_relaxed(val, clk_data->base + REG_SUBBLK_RESET_CR); + + dev_dbg(clk_data->dev, "deassert reset: %02lu\n", id); + + return 0; +} + +static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long i= d) +{ + struct mpfs_clock_data *clk_data =3D rcdev_to_clock_data(rcdev); + u32 reg; + + reg =3D readl_relaxed(clk_data->base + REG_SUBBLK_RESET_CR); + return (reg & (1u << id)); +} + + // .reset =3D mpfs_reset, +static const struct reset_control_ops mpfs_reset_ops =3D { + .assert =3D mpfs_assert, + .deassert =3D mpfs_deassert, + .status =3D mpfs_status, +}; + +//geert - does it make sense to reuse the clk_ indexes for the reset ctrlr? +// -> they run from 3 to 32 but skip one +//if yes, do i p much just subtract 3 in of_xlate & manipulate that bit? +static int mpfs_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct mpfs_clock_data *clk_data =3D rcdev_to_clock_data(rcdev); + unsigned int index =3D reset_spec->args[0]; + /* account for reserved fpga fabric reset */ + unsigned int num_resets =3D ARRAY_SIZE(mpfs_periph_clks) + 1; + + if (index < MPFS_PERIPH_OFFSET || index > (MPFS_PERIPH_OFFSET + num= _resets)) { + dev_err(clk_data->dev, "Invalid reset index %u\n", reset_sp= ec->args[0]); + return -EINVAL; + } + + return index - MPFS_PERIPH_OFFSET; +} +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + clk_data->rcdev.ops =3D &mpfs_reset_ops; + clk_data->rcdev.of_node =3D clk_data->dev->of_node; + clk_data->rcdev.of_reset_n_cells =3D 1; + clk_data->rcdev.of_xlate =3D mpfs_reset_xlate; + /* CLK_RESERVED is not part of mpfs_periph_clks, so add 1 */ + clk_data->rcdev.nr_resets =3D ARRAY_SIZE(mpfs_periph_clks) + 1; + return devm_reset_controller_register(clk_data->dev, &clk_data->rcd= ev); +} + +#else /* !CONFIG_RESET_CONTROLLER */ +static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data) +{ + return 0; +} +#endif /* !CONFIG_RESET_CONTROLLER */ + static int mpfs_clk_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -496,6 +608,7 @@ static int mpfs_clk_probe(struct platform_device *pdev) return PTR_ERR(clk_data->msspll_base); =20 clk_data->hw_data.num =3D num_clks; + clk_data->dev =3D dev; =20 ret =3D mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE= (mpfs_msspll_clks), clk_data); @@ -515,6 +628,10 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; =20 + ret =3D mpfs_reset_controller_register(clk_data); + if (ret) + return ret; + return ret; }