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[93.144.20.233]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b91942e52sm8831016f8f.9.2026.03.26.08.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 08:48:27 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shawn Guo , Dario Binacchi , Alexander Stein , Maud Spierings , Josua Mayer , Markus Niebel , Francesco Dolcini , Primoz Fiser Subject: [PATCH v1 2/3] arm64: dts: freescale: Add support for Variscite DART-MX93 Date: Thu, 26 Mar 2026 16:47:18 +0100 Message-ID: <304e5edc9ed11a552ac96c28d1046e4b13d5f960.1774539301.git.stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefano Radaelli Add device tree support for the Variscite DART-MX93 system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX93 MPU processor - Up to 2GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-93/dart-mx93/ Signed-off-by: Stefano Radaelli --- .../boot/dts/freescale/imx93-var-dart.dtsi | 462 ++++++++++++++++++ 1 file changed, 462 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx93-var-dart.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx93-var-dart.dtsi b/arch/arm64= /boot/dts/freescale/imx93-var-dart.dtsi new file mode 100644 index 000000000000..bfed6625f5ab --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-var-dart.dtsi @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Common dtsi for Variscite DART-MX93 + * + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-93/dart-mx= 93/ + * + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include "imx93.dtsi" + +/ { + model =3D "Variscite DART-MX93 Module"; + compatible =3D "variscite,var-dart-mx93", "fsl,imx93"; + + sound-wm8904 { + compatible =3D "simple-audio-card"; + simple-audio-card,bitclock-master =3D <&codec_dai>; + simple-audio-card,format =3D "i2s"; + simple-audio-card,frame-master =3D <&codec_dai>; + simple-audio-card,mclk-fs =3D <256>; + simple-audio-card,name =3D "wm8904-audio"; + simple-audio-card,routing =3D + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets =3D + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai =3D <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai =3D <&sai1>; + }; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <10000>; + reset-gpios =3D <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ + <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ + }; +}; + +&cm33 { + mbox-names =3D "tx", "rx", "rxdb"; + mboxes =3D <&mu1 0 1>, + <&mu1 1 1>, + <&mu1 3 1>; + memory-region =3D <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; + status =3D "okay"; +}; + +&eqos { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_eqos>; + pinctrl-1 =3D <&pinctrl_eqos_sleep>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <ðphy0>; + snps,clk-csr =3D <5>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + clock-frequency =3D <1000000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + ethphy0: ethernet-phy@0 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0>; + reset-gpios =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <100000>; + }; + }; +}; + +&lpi2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default", "sleep", "gpio"; + pinctrl-0 =3D <&pinctrl_lpi2c3>; + pinctrl-1 =3D <&pinctrl_lpi2c3_gpio>; + pinctrl-2 =3D <&pinctrl_lpi2c3_gpio>; + scl-gpios =3D <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios =3D <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status =3D "okay"; + + wm8904: audio-codec@1a { + compatible =3D "wlf,wm8904"; + reg =3D <0x1a>; + #sound-dai-cells =3D <0>; + clocks =3D <&clk IMX93_CLK_SAI1_GATE>; + clock-names =3D "mclk"; + AVDD-supply =3D <&buck5>; + CPVDD-supply =3D <&buck5>; + DBVDD-supply =3D <&buck4>; + DCVDD-supply =3D <&buck5>; + MICVDD-supply =3D <&buck5>; + wlf,drc-cfg-names =3D "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP =3D 0, KNEE_OP =3D 0, HI_COMP =3D 1, LO_COMP =3D 1 + * KNEE_IP =3D -24, KNEE_OP =3D -6, HI_COMP =3D 1/4, LO_COMP =3D 1 + * KNEE_IP =3D -42, KNEE_OP =3D -3, HI_COMP =3D 0, LO_COMP =3D 1 + * KNEE_IP =3D -45, KNEE_OP =3D -9, HI_COMP =3D 1/8, LO_COMP =3D 1 + * KNEE_IP =3D -30, KNEE_OP =3D -10.5, HI_COMP =3D 1/4, LO_COMP =3D 1 + */ + wlf,drc-cfg-regs =3D /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 =3D DMIC_CLK, don't touch others */ + wlf,gpio-cfg =3D <0x0018>, <0xffff>, <0xffff>, <0xffff>; + /* DMIC is connected to IN1L */ + wlf,in1l-as-dmicdat1; + }; + + pmic@25 { + compatible =3D "nxp,pca9451a"; + reg =3D <0x25>; + + regulators { + buck1: BUCK1 { + regulator-name =3D "BUCK1"; + regulator-min-microvolt =3D <650000>; + regulator-max-microvolt =3D <2237500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck2: BUCK2 { + regulator-name =3D "BUCK2"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay =3D <3125>; + }; + + buck4: BUCK4 { + regulator-name =3D "BUCK4"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name =3D "BUCK5"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name =3D "BUCK6"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name =3D "LDO1"; + regulator-min-microvolt =3D <1600000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name =3D "LDO4"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name =3D "LDO5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +/* BT module */ +&lpuart5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart5>, <&pinctrl_bt>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "nxp,88w8987-bt"; + }; +}; + +&mu1 { + status =3D "okay"; +}; + +&mu2 { + status =3D "okay"; +}; + +&sai1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pinctrl_sai1>; + pinctrl-1 =3D <&pinctrl_sai1_sleep>; + assigned-clocks =3D <&clk IMX93_CLK_SAI1>; + assigned-clock-parents =3D <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates =3D <12288000>; + #sound-dai-cells =3D <0>; + fsl,sai-mclk-direction-output; + status =3D "okay"; +}; + +/* eMMC */ +&usdhc1 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc1>; + pinctrl-1 =3D <&pinctrl_usdhc1_100mhz>; + pinctrl-2 =3D <&pinctrl_usdhc1_200mhz>; + bus-width =3D <8>; + non-removable; + status =3D "okay"; +}; + +/* WiFi */ +&usdhc3 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 =3D <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>; + pinctrl-3 =3D <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>; + mmc-pwrseq =3D <&wifi_pwrseq>; + keep-power-in-suspend; + bus-width =3D <4>; + non-removable; + wakeup-source; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_bt: btgrp { + fsl,pins =3D < + MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins =3D < + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e + >; + }; + + pinctrl_eqos_sleep: eqos-sleepgrp { + fsl,pins =3D < + MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e + MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e + MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e + MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e + MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e + MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e + MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e + MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e + MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e + MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e + MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e + MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e + MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e + MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins =3D < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins =3D < + MX93_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e + MX93_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins =3D < + MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e + MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e + MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e + MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e + MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e + MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e + MX93_PAD_UART2_RXD__SAI1_MCLK 0x31e + >; + }; + + pinctrl_sai1_sleep: sai1-sleepgrp { + fsl,pins =3D < + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x31e + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x31e + MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x31e + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x31e + MX93_PAD_UART2_RXD__GPIO1_IO06 0x31e + MX93_PAD_I2C2_SDA__GPIO1_IO03 0x31e + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins =3D < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins =3D < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins =3D < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins =3D < + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x1582 + MX93_PAD_SD3_CMD__USDHC3_CMD 0x40001382 + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x40001382 + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x40001382 + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x40001382 + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x40001382 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x158e + MX93_PAD_SD3_CMD__USDHC3_CMD 0x4000138e + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x4000138e + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x4000138e + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x4000138e + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x4000138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX93_PAD_SD3_CLK__USDHC3_CLK 0x15fe + MX93_PAD_SD3_CMD__USDHC3_CMD 0x400013fe + MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x400013fe + MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x400013fe + MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x400013fe + MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x400013fe + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins =3D < + MX93_PAD_SD3_CLK__GPIO3_IO20 0x400 + MX93_PAD_SD3_CMD__GPIO3_IO21 0x400 + MX93_PAD_SD3_DATA0__GPIO3_IO22 0x400 + MX93_PAD_SD3_DATA1__GPIO3_IO23 0x400 + MX93_PAD_SD3_DATA2__GPIO3_IO24 0x400 + MX93_PAD_SD3_DATA3__GPIO3_IO25 0x400 + >; + }; + + pinctrl_usdhc3_wlan: usdhc3wlangrp { + fsl,pins =3D < + MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x51e + >; + }; +}; --=20 2.47.3