From nobody Sun Apr 5 19:49:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66EE237FF66 for ; Wed, 1 Apr 2026 04:58:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019482; cv=none; b=fuR42H2Z+NBUBUttBPVD33OBTQ9EGcsRKajbQ5pBNy8Pj6PwLgp2nqJ9+tGriMNQgAqfV1T4GVS74jg/zeSmMQGSGOiVZad5nlwG6ZoEFlt4ihChhoIbzAHFz2cS95JCUKfu0zoHNgFjqqkIhA308tv+WRKhwJQw+nTApqJrdbw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019482; c=relaxed/simple; bh=mhMkiLJ2AM2h6N0ira9zkE5d1/7knLpaBSGY4Xr35UQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I4TBD07s/MT3LSTmVk17JAsGNvcp1/pCZMTAmRbHEcWt9fNoBrkzVSBastJ/ezntKgLfg5Rg88HtOkIqrmdusqD7e2cDt4+TakNEuDLTPa5PKMhsLgvlTf1d6GnFe9jALCYXDnAKUo6AykkMtKzr+Ja13MO0DrK+4o6vLW0V1xo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D5QPvPFv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D5QPvPFv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1FA5AC2BCB3; Wed, 1 Apr 2026 04:58:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775019482; bh=mhMkiLJ2AM2h6N0ira9zkE5d1/7knLpaBSGY4Xr35UQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D5QPvPFvT8TRArCvjic2+k11ExiHEtnCSh4rRS+m22isQT7hqMf9UCEE2mJFJGo/8 Zxnv63Z4Fsgweuk+/uOYBlM+423U1vby1kqbpeA7AZKMjFnZSvEaNwuqmb63PNnlkk Wioteh3jXkjHW6nqkbTIgouAcg8gFhKZU5bSO/DLiqjtFRhIzQgNOd/lXcsrM8Bbat g8EkRASvnBZ2m2FFssIeV0gUSprtqdnWokFI/xLZzOesfZoRGldRdrVps04phLmylf W8sutFsqYS/zYJz0DDpUj4YoLZfnYfY1k9pINfu63UmZZkkVvjvM5VMM4FLJ+rYf3C pZ/uKM93pN60g== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao Subject: [PATCH 5/5] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count Date: Wed, 1 Apr 2026 10:26:36 +0530 Message-ID: <2fd862367e1552615c823a6cda274b05bc04cc38.1775019269.git.naveen@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Switch to using apic_eilvt_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. But do so during init instead of in reserve_eilvt_offset() since the latter is called with preemption disabled. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H =20 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 748e09c5b322..c4dfd7e93fe4 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -340,7 +340,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int = oneshot, int irqen) * necessarily a BIOS bug. */ =20 -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; unsigned int apic_eilvt_count __ro_after_init; EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count); =20 @@ -355,7 +355,7 @@ static unsigned int reserve_eilvt_offset(int offset, un= signed int new) { unsigned int rsvd, vector; =20 - if (offset >=3D APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >=3D apic_eilvt_count) return ~0; =20 rsvd =3D atomic_read(&eilvt_offsets[offset]); @@ -418,6 +418,9 @@ static __init void init_eilvt(void) =20 if (!apic_eilvt_count) apic_eilvt_count =3D APIC_EILVT_NR_AMD_10H; + + if (!eilvt_offsets) + eilvt_offsets =3D kzalloc_objs(atomic_t, apic_eilvt_count); } =20 /* --=20 2.53.0