From nobody Fri Apr 3 16:04:49 2026 Received: from www537.your-server.de (www537.your-server.de [188.40.3.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66C573F87FF; Tue, 24 Mar 2026 12:30:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=188.40.3.216 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774355429; cv=none; b=OI1/xD7KxMwzu7Z8IFzfV5V0eVyDnJAzOe5uGshi1e2EA++ug8nGdmnPlMMc7apuWEE3HT/29BYWbz3z9+t6UZBzCOwZ6Fu25YraQe9mh6HZ8pN8ru1ANhj/9zDB5kViZzCS6Jti4TudxoumHLDE6yTQ4Kp2tU9paBAJClBMiGs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774355429; c=relaxed/simple; bh=jcplQi3Mocc1VLQA6H9ineVeTMeOKfBlXqPAmboXcHo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dbM0QM1j6nUPyjM+TMq6xVUbz/2vF16EyUy0CL9orCaNDplog/MPQ0EFs/Iod+F10YISlfZCWyQTr6qMZyCdmYcdOquM5T7+9sQJ1VRzJMD/UNWjEFvKhFwLW0rXrhSFRgsGz+7Dyy1jPI1PGBMaKLyTo3Nw5cXNGErK22gxSB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ew.tq-group.com; spf=pass smtp.mailfrom=ew.tq-group.com; dkim=pass (2048-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b=c76tjtOf; arc=none smtp.client-ip=188.40.3.216 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ew.tq-group.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ew.tq-group.com header.i=@ew.tq-group.com header.b="c76tjtOf" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=ew.tq-group.com; s=default2602; h=Content-Transfer-Encoding:Content-Type: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID; bh=KqcLRKudHgKSmtkMDFCAvoKWKKoLB9Rc1nid7QyUgsk=; b=c76tjtOf9ZadDn52buaIMXYV9x I3eh3Ugqpq5lz/jLCzFReaKfl/3oZh6fCQas8DZU7GjxfkFu4j8uAkpIfWr9c7qtk+CK5xW6zrfUA ADBXdZTWSh3e/FeNjpTckiSLhzxmI2DxK7iTXaXE7XglyuAgMJ4AZkP0oV3BtHc7NeCuQMhrOGPAQ dzGYHyvblvMy6fi3tWQP6HH8/rlGVDsVwGm5Y2zniBg0/U9geuCP2J0y20pd8QFFxRZdXeucSU24W PZOAdKXbVG0mhbvHTO6of1VvcPxP74wto3ytmI4kA+gEoOkHn8ailBGaPZm4kmeFAu1U4rtYwRC9o 91AVNbCQ==; Received: from sslproxy05.your-server.de ([78.46.172.2]) by www537.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1w50tr-0005qM-2r; Tue, 24 Mar 2026 13:30:23 +0100 Received: from localhost ([127.0.0.1]) by sslproxy05.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1w50tr-000Pna-2M; Tue, 24 Mar 2026 13:30:23 +0100 From: Nora Schiffer To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Nishanth Menon , Vignesh Raghavendra , Tero Kristo Cc: Siddharth Vadapalli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul , Neil Armstrong , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux@ew.tq-group.com, Nora Schiffer Subject: [PATCH v2 4/7] phy: ti: phy-j721e-wiz: add support for J722S SoC family Date: Tue, 24 Mar 2026 13:29:40 +0100 Message-ID: <2e7975baed312b8428199a88e92be47442af964f.1774354734.git.nora.schiffer@ew.tq-group.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: Clear (ClamAV 1.4.3/27950/Tue Mar 24 07:24:19 2026) The J722S WIZ is mostly identical to the AM64's, but additionally supports SGMII. Signed-off-by: Nora Schiffer --- drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 6b584706b913a..7531a8a049123 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -331,6 +331,7 @@ enum wiz_type { J721E_WIZ_16G, J721E_WIZ_10G, /* Also for J7200 SR1.0 */ AM64_WIZ_10G, + J722S_WIZ_10G, J7200_WIZ_10G, /* J7200 SR2.0 */ J784S4_WIZ_10G, J721S2_WIZ_10G, @@ -1020,6 +1021,7 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct= device_node *node) =20 switch (wiz->type) { case AM64_WIZ_10G: + case J722S_WIZ_10G: case J7200_WIZ_10G: case J784S4_WIZ_10G: case J721S2_WIZ_10G: @@ -1089,6 +1091,7 @@ static void wiz_clock_init(struct wiz *wiz) =20 switch (wiz->type) { case AM64_WIZ_10G: + case J722S_WIZ_10G: case J7200_WIZ_10G: switch (rate) { case REF_CLK_100MHZ: @@ -1158,6 +1161,7 @@ static int wiz_clock_probe(struct wiz *wiz, struct de= vice_node *node) =20 switch (wiz->type) { case AM64_WIZ_10G: + case J722S_WIZ_10G: case J7200_WIZ_10G: case J784S4_WIZ_10G: case J721S2_WIZ_10G: @@ -1246,6 +1250,14 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int l= ane) if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_SGMII) return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); break; + + case J722S_WIZ_10G: + if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_PCIE) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1); + if (wiz->lane_phy_type[lane] =3D=3D PHY_TYPE_SGMII) + return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2); + break; + default: return 0; } @@ -1350,6 +1362,15 @@ static struct wiz_data am64_10g_data =3D { .clk_div_sel_num =3D WIZ_DIV_NUM_CLOCKS_10G, }; =20 +static struct wiz_data j722s_10g_data =3D { + .type =3D J722S_WIZ_10G, + .pll0_refclk_mux_sel =3D &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel =3D &pll1_refclk_mux_sel, + .refclk_dig_sel =3D &refclk_dig_sel_10g, + .clk_mux_sel =3D clk_mux_sel_10g, + .clk_div_sel_num =3D WIZ_DIV_NUM_CLOCKS_10G, +}; + static struct wiz_data j7200_pg2_10g_data =3D { .type =3D J7200_WIZ_10G, .pll0_refclk_mux_sel =3D &sup_pll0_refclk_mux_sel, @@ -1389,6 +1410,9 @@ static const struct of_device_id wiz_id_table[] =3D { { .compatible =3D "ti,am64-wiz-10g", .data =3D &am64_10g_data, }, + { + .compatible =3D "ti,j722s-wiz-10g", .data =3D &j722s_10g_data, + }, { .compatible =3D "ti,j7200-wiz-10g", .data =3D &j7200_pg2_10g_data, }, --=20 TQ-Systems GmbH | M=C3=BChlstra=C3=9Fe 2, Gut Delling | 82229 Seefeld, Germ= any Amtsgericht M=C3=BCnchen, HRB 105018 Gesch=C3=A4ftsf=C3=BChrer: Detlef Schneider, R=C3=BCdiger Stahl, Stefan Sch= neider https://www.tq-group.com/