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Fri, 27 Feb 2026 16:55:39 -0800 (PST) Date: Fri, 27 Feb 2026 21:55:33 -0300 From: Geraldo Nascimento To: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Geraldo Nascimento , Dragan Simic Cc: linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 3/4] PCI: rockchip: drive at 2.5 GT/s, error other speeds Message-ID: <2a0a4aa97bb8b0cb511cb651c5d66c9ec8bab97a.1772239598.git.geraldogabriel@gmail.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Configure the core to be driven at 2.5 GT/s Link Speed and ignore any other speed with a warning. The reason is that Shawn Lin from Rockchip has reiterated that there may be danger of "catastrophic failure" in using their PCIe with 5.0 GT/s speeds. While Rockchip has done so informally without issuing a proper errata, and the particulars are thus unknown, this may cause data loss or worse. This change is corroborated by RK3399 official datasheet [1], which states maximum link speed for this platform is 2.5 GT/s. [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet= _V2.1-20200323.pdf Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock= -chips.com/ Cc: stable@vger.kernel.org Reported-by: Dragan Simic Reported-by: Shawn Lin Signed-off-by: Geraldo Nascimento --- drivers/pci/controller/pcie-rockchip.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controlle= r/pcie-rockchip.c index 0f88da378805..2f211d1f4c7c 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -66,8 +66,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchi= p) } =20 rockchip->link_gen =3D of_pci_get_max_link_speed(node); - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) - rockchip->link_gen =3D 2; + if (rockchip->link_gen < 0 || rockchip->link_gen >=3D 2) { + rockchip->link_gen =3D 1; + dev_warn(dev, "invalid max-link-speed, fix your DT\n"); + } =20 for (i =3D 0; i < ROCKCHIP_NUM_PM_RSTS; i++) rockchip->pm_rsts[i].id =3D rockchip_pci_pm_rsts[i]; @@ -147,12 +149,13 @@ int rockchip_pcie_init_port(struct rockchip_pcie *roc= kchip) goto err_exit_phy; } =20 - if (rockchip->link_gen =3D=3D 2) - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, - PCIE_CLIENT_CONFIG); - else + if (rockchip->link_gen =3D=3D 2) { + /* 5.0 GT/s may cause catastrophic failure for this core */ + dev_warn(dev, "5.0 GT/s may cause data loss or worse\n"); + } else { rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, PCIE_CLIENT_CONFIG); + } =20 regs =3D PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); --=20 2.52.0