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[79.33.140.232]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4888a63c9b1sm141359835e9.5.2026.04.03.07.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Apr 2026 07:28:59 -0700 (PDT) From: Andrea della Porta To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list , Andrea della Porta , devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Naushir Patuck , Stanimir Varbanov Subject: [PATCH 2/3] pwm: rp1: Add RP1 PWM controller driver Date: Fri, 3 Apr 2026 16:31:55 +0200 Message-ID: <28e29fbfc20c0b8a115d006233c2759d8f49e639.1775223441.git.andrea.porta@suse.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Naushir Patuck The Raspberry Pi RP1 southbridge features an embedded PWM controller with 4 output channels, alongside an RPM interface to read the fan speed on the Raspberry Pi 5. Add the supporting driver. Signed-off-by: Naushir Patuck Co-developed-by: Stanimir Varbanov Signed-off-by: Stanimir Varbanov Signed-off-by: Andrea della Porta --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-rp1.c | 244 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 255 insertions(+) create mode 100644 drivers/pwm/pwm-rp1.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 6f3147518376a..22e4fc6385da2 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -625,6 +625,16 @@ config PWM_ROCKCHIP Generic PWM framework driver for the PWM controller found on Rockchip SoCs. =20 +config PWM_RP1 + tristate "RP1 PWM support" + depends on MISC_RP1 || COMPILE_TEST + depends on HWMON + help + PWM framework driver for Raspberry Pi RP1 controller + + To compile this driver as a module, choose M here: the module + will be called pwm-rp1. + config PWM_SAMSUNG tristate "Samsung PWM support" depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 0dc0d2b69025d..895a7c42fe9c0 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_PWM_RENESAS_RZG2L_GPT) +=3D pwm-rzg2l-gpt.o obj-$(CONFIG_PWM_RENESAS_RZ_MTU3) +=3D pwm-rz-mtu3.o obj-$(CONFIG_PWM_RENESAS_TPU) +=3D pwm-renesas-tpu.o obj-$(CONFIG_PWM_ROCKCHIP) +=3D pwm-rockchip.o +obj-$(CONFIG_PWM_RP1) +=3D pwm-rp1.o obj-$(CONFIG_PWM_SAMSUNG) +=3D pwm-samsung.o obj-$(CONFIG_PWM_SIFIVE) +=3D pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) +=3D pwm-sl28cpld.o diff --git a/drivers/pwm/pwm-rp1.c b/drivers/pwm/pwm-rp1.c new file mode 100644 index 0000000000000..0a1c1c1dd27e9 --- /dev/null +++ b/drivers/pwm/pwm-rp1.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pwm-rp1.c + * + * Raspberry Pi RP1 PWM. + * + * Copyright =C2=A9 2026 Raspberry Pi Ltd. + * + * Author: Naushir Patuck (naush@raspberrypi.com) + * + * Based on the pwm-bcm2835 driver by: + * Bart Tanghe + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PWM_GLOBAL_CTRL 0x000 +#define PWM_CHANNEL_CTRL(x) (0x014 + ((x) * 0x10)) +#define PWM_RANGE(x) (0x018 + ((x) * 0x10)) +#define PWM_PHASE(x) (0x01C + ((x) * 0x10)) +#define PWM_DUTY(x) (0x020 + ((x) * 0x10)) + +/* 8:FIFO_POP_MASK + 0:Trailing edge M/S modulation */ +#define PWM_CHANNEL_DEFAULT (BIT(8) + BIT(0)) +#define PWM_CHANNEL_ENABLE(x) BIT(x) +#define PWM_POLARITY BIT(3) +#define SET_UPDATE BIT(31) +#define PWM_MODE_MASK GENMASK(1, 0) + +#define NUM_PWMS 4 + +struct rp1_pwm { + void __iomem *base; + struct clk *clk; +}; + +static const struct hwmon_channel_info * const rp1_fan_hwmon_info[] =3D { + HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT), + NULL +}; + +static umode_t rp1_fan_hwmon_is_visible(const void *data, enum hwmon_senso= r_types type, + u32 attr, int channel) +{ + umode_t mode =3D 0; + + if (type =3D=3D hwmon_fan && attr =3D=3D hwmon_fan_input) + mode =3D 0444; + + return mode; +} + +static int rp1_fan_hwmon_read(struct device *dev, enum hwmon_sensor_types = type, + u32 attr, int channel, long *val) +{ + struct rp1_pwm *rp1 =3D dev_get_drvdata(dev); + + if (type !=3D hwmon_fan || attr !=3D hwmon_fan_input) + return -EOPNOTSUPP; + + *val =3D readl(rp1->base + PWM_PHASE(2)); + + return 0; +} + +static const struct hwmon_ops rp1_fan_hwmon_ops =3D { + .is_visible =3D rp1_fan_hwmon_is_visible, + .read =3D rp1_fan_hwmon_read, +}; + +static const struct hwmon_chip_info rp1_fan_hwmon_chip_info =3D { + .ops =3D &rp1_fan_hwmon_ops, + .info =3D rp1_fan_hwmon_info, +}; + +static void rp1_pwm_apply_config(struct pwm_chip *chip, struct pwm_device = *pwm) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + u32 value; + + value =3D readl(rp1->base + PWM_GLOBAL_CTRL); + value |=3D SET_UPDATE; + writel(value, rp1->base + PWM_GLOBAL_CTRL); +} + +static int rp1_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + + writel(PWM_CHANNEL_DEFAULT, rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm)); + return 0; +} + +static void rp1_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + u32 value; + + value =3D readl(rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm)); + value &=3D ~PWM_MODE_MASK; + writel(value, rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm)); + + rp1_pwm_apply_config(chip, pwm); +} + +static int rp1_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct rp1_pwm *rp1 =3D pwmchip_get_drvdata(chip); + unsigned long clk_rate =3D clk_get_rate(rp1->clk); + unsigned long clk_period; + u32 value; + + if (!clk_rate) { + dev_err(&chip->dev, "failed to get clock rate\n"); + return -EINVAL; + } + + /* set period and duty cycle */ + clk_period =3D DIV_ROUND_CLOSEST(NSEC_PER_SEC, clk_rate); + + writel(DIV_ROUND_CLOSEST(state->duty_cycle, clk_period), + rp1->base + PWM_DUTY(pwm->hwpwm)); + + writel(DIV_ROUND_CLOSEST(state->period, clk_period), + rp1->base + PWM_RANGE(pwm->hwpwm)); + + /* set polarity */ + value =3D readl(rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm)); + if (state->polarity =3D=3D PWM_POLARITY_NORMAL) + value &=3D ~PWM_POLARITY; + else + value |=3D PWM_POLARITY; + writel(value, rp1->base + PWM_CHANNEL_CTRL(pwm->hwpwm)); + + /* enable/disable */ + value =3D readl(rp1->base + PWM_GLOBAL_CTRL); + if (state->enabled) + value |=3D PWM_CHANNEL_ENABLE(pwm->hwpwm); + else + value &=3D ~PWM_CHANNEL_ENABLE(pwm->hwpwm); + writel(value, rp1->base + PWM_GLOBAL_CTRL); + + rp1_pwm_apply_config(chip, pwm); + + return 0; +} + +static const struct pwm_ops rp1_pwm_ops =3D { + .request =3D rp1_pwm_request, + .free =3D rp1_pwm_free, + .apply =3D rp1_pwm_apply, +}; + +static int rp1_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device *hwmon_dev; + struct pwm_chip *chip; + struct rp1_pwm *rp1; + int ret; + + chip =3D devm_pwmchip_alloc(dev, NUM_PWMS, sizeof(*rp1)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + rp1 =3D pwmchip_get_drvdata(chip); + + rp1->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rp1->base)) + return PTR_ERR(rp1->base); + + rp1->clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(rp1->clk)) + return dev_err_probe(dev, PTR_ERR(rp1->clk), "clock not found\n"); + + ret =3D devm_clk_rate_exclusive_get(dev, rp1->clk); + if (ret) + return dev_err_probe(dev, ret, "fail to get exclusive rate\n"); + + chip->ops =3D &rp1_pwm_ops; + + platform_set_drvdata(pdev, chip); + + ret =3D devm_pwmchip_add(dev, chip); + if (ret) + return dev_err_probe(dev, ret, "failed to register PWM chip\n"); + + hwmon_dev =3D devm_hwmon_device_register_with_info(dev, "rp1_fan_tach", r= p1, + &rp1_fan_hwmon_chip_info, + NULL); + + if (IS_ERR(hwmon_dev)) + return dev_err_probe(dev, PTR_ERR(hwmon_dev), + "failed to register hwmon fan device\n"); + + return 0; +} + +static int rp1_pwm_suspend(struct device *dev) +{ + struct rp1_pwm *rp1 =3D dev_get_drvdata(dev); + + clk_disable_unprepare(rp1->clk); + + return 0; +} + +static int rp1_pwm_resume(struct device *dev) +{ + struct rp1_pwm *rp1 =3D dev_get_drvdata(dev); + + return clk_prepare_enable(rp1->clk); +} + +static DEFINE_SIMPLE_DEV_PM_OPS(rp1_pwm_pm_ops, rp1_pwm_suspend, rp1_pwm_r= esume); + +static const struct of_device_id rp1_pwm_of_match[] =3D { + { .compatible =3D "raspberrypi,rp1-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rp1_pwm_of_match); + +static struct platform_driver rp1_pwm_driver =3D { + .probe =3D rp1_pwm_probe, + .driver =3D { + .name =3D "rp1-pwm", + .of_match_table =3D rp1_pwm_of_match, + .pm =3D pm_ptr(&rp1_pwm_pm_ops), + }, +}; +module_platform_driver(rp1_pwm_driver); + +MODULE_DESCRIPTION("RP1 PWM driver"); +MODULE_AUTHOR("Naushir Patuck "); +MODULE_LICENSE("GPL"); --=20 2.35.3