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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 01:24:58.9017 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ed9fb169-55ff-4343-1fac-08de59550ee9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000147.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6873 Content-Type: text/plain; charset="utf-8" VMM needs a domain holding the mappings between gPA to hPA. It can be an S1 domain or an S2 nesting parent domain, depending on whether the VM is built with a vSMMU or not. Given that the IOAS for this gPA mapping is the same across SMMU instances, this domain can be shared across devices even if they sit behind different SMMUs, so long as the underlying page table is compatible between the SMMU instances. There is no direct information about the page table from the master device, but a comparison can be done between the physical SMMU that the domain was allocated for and the physical SMMU that the device is behind. Replace the smmu test in arm_smmu_attach_dev() and arm_vsmmu_init() with a compatibility test for the S1 and S2 cases respectively. The compatibility test goes through the physical SMMU parameters that were used to decide the page table formats. Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 20 +++++++++++++++++++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 2 +- 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index c7b054eb062a..c4bea9f7f4f1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -982,6 +982,26 @@ struct arm_smmu_nested_domain { __le64 ste[2]; }; =20 +static inline bool +arm_smmu_domain_can_share(struct arm_smmu_domain *smmu_domain, + struct arm_smmu_device *new_smmu) +{ + struct arm_smmu_device *base_smmu =3D smmu_domain->smmu; + + if (base_smmu =3D=3D new_smmu) + return true; + /* Only support identical SMMUs for now */ + if (base_smmu->features !=3D new_smmu->features) + return false; + if (base_smmu->iommu.ops !=3D new_smmu->iommu.ops) + return false; + if (base_smmu->pgsize_bitmap !=3D new_smmu->pgsize_bitmap) + return false; + if (base_smmu->ias > new_smmu->ias || base_smmu->oas > new_smmu->oas) + return false; + return true; +} + /* The following are exposed for testing purposes. */ struct arm_smmu_entry_writer_ops; struct arm_smmu_entry_writer { diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 33b336d494c3..6ecf98ca3bb8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -467,7 +467,7 @@ int arm_vsmmu_init(struct iommufd_viommu *viommu, struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent_domain); int id; =20 - if (s2_parent->smmu !=3D smmu) + if (!arm_smmu_domain_can_share(s2_parent, smmu)) return -EINVAL; =20 mutex_lock(&arm_smmu_asid_lock); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 19437ee6f4e1..4252418fc0a9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -3635,7 +3635,7 @@ static int arm_smmu_attach_dev(struct iommu_domain *d= omain, struct device *dev, state.master =3D master =3D dev_iommu_priv_get(dev); smmu =3D master->smmu; =20 - if (smmu_domain->smmu !=3D smmu) + if (!arm_smmu_domain_can_share(smmu_domain, smmu)) return -EINVAL; =20 if (smmu_domain->stage =3D=3D ARM_SMMU_DOMAIN_S1) { --=20 2.43.0