From nobody Mon Jun 15 00:21:34 2026 Received: from mailgw.kylinos.cn (mailgw.kylinos.cn [124.126.103.232]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE68C3A6EEF; Tue, 7 Apr 2026 09:55:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=124.126.103.232 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775555721; cv=none; b=kxrHa46z3uJUuL/2MKOsGqVMFqXDe2tplqwcoEVqwzNaxDJhMVzgVMg6IwfNb8BdMQN8dNU8zf7+id18M4U+no4sfiHJA2NWX8PeJ446L/OtmC4XAr7AAL6CieTd/UVavMbF/mACJTpNs+ORbTw7TgiDQtIeTHvbhjyFhyBdc5s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775555721; c=relaxed/simple; bh=eJjFVTIXUOF6lowGtHozeXY5aQhNpvhp9YIBRdayF00=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=bfwA3w61m41hfPD2MApMnQgFJi3B1lsX0rO6DhK1P3FXk1+rTYdg0cTPOqUnrcbJlmcGz4ejPBFmRzl++Kgha/u+VpoVZwJ3s/PANYln2lLM5Bl49BXNb718Z+tQS00gsbEp1LeAhjjg1Ws+++Z81r3BBMrRBhkPfYsq19jecUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn; spf=pass smtp.mailfrom=kylinos.cn; arc=none smtp.client-ip=124.126.103.232 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=kylinos.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=kylinos.cn X-UUID: debe54c2326711f1aa26b74ffac11d73-20260407 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:b225edfa-ba44-44c5-8059-5a446069d6c3,IP:0,U RL:0,TC:0,Content:-25,EDM:25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:be64a76979a2535dc400280771fa8ebf,BulkI D:nil,BulkQuantity:0,Recheck:0,SF:102|850|898,TC:nil,Content:0|15|50,EDM:5 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: debe54c2326711f1aa26b74ffac11d73-20260407 X-User: xiaopei01@kylinos.cn Received: from localhost.localdomain [(10.44.16.150)] by mailgw.kylinos.cn (envelope-from ) (Generic MTA with TLSv1.3 TLS_AES_256_GCM_SHA384 256/256) with ESMTP id 242420818; Tue, 07 Apr 2026 17:55:12 +0800 From: Pei Xiao To: michal.simek@amd.com, broonie@kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Pei Xiao Subject: [PATCH V2] spi: zynq-qspi: Simplify clock handling with devm_clk_get_enabled() Date: Tue, 7 Apr 2026 17:55:08 +0800 Message-Id: <24043625f89376da36feca2408f990a85be7ab36.1775555500.git.xiaopei01@kylinos.cn> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace devm_clk_get() followed by clk_prepare_enable() with devm_clk_get_enabled() for both "pclk" and "ref_clk". This removes the need for explicit clock enable and disable calls, as the managed API automatically disables the clocks on device removal or probe failure. Remove the now-unnecessary clk_disable_unprepare() calls from the probe error paths and the remove callback. Simplify error handling by jumping directly to the remove_ctlr label. Signed-off-by: Pei Xiao Acked-by: Michal Simek --- changlog in v2: remove clk enable in setup_op function --- drivers/spi/spi-zynq-qspi.c | 42 ++++++------------------------------- 1 file changed, 6 insertions(+), 36 deletions(-) diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c index 5232483c4a3a..af252500195c 100644 --- a/drivers/spi/spi-zynq-qspi.c +++ b/drivers/spi/spi-zynq-qspi.c @@ -381,21 +381,10 @@ static int zynq_qspi_setup_op(struct spi_device *spi) { struct spi_controller *ctlr =3D spi->controller; struct zynq_qspi *qspi =3D spi_controller_get_devdata(ctlr); - int ret; =20 if (ctlr->busy) return -EBUSY; =20 - ret =3D clk_enable(qspi->refclk); - if (ret) - return ret; - - ret =3D clk_enable(qspi->pclk); - if (ret) { - clk_disable(qspi->refclk); - return ret; - } - zynq_qspi_write(qspi, ZYNQ_QSPI_ENABLE_OFFSET, ZYNQ_QSPI_ENABLE_ENABLE_MASK); =20 @@ -661,7 +650,7 @@ static int zynq_qspi_probe(struct platform_device *pdev) goto remove_ctlr; } =20 - xqspi->pclk =3D devm_clk_get(&pdev->dev, "pclk"); + xqspi->pclk =3D devm_clk_get_enabled(&pdev->dev, "pclk"); if (IS_ERR(xqspi->pclk)) { dev_err(&pdev->dev, "pclk clock not found.\n"); ret =3D PTR_ERR(xqspi->pclk); @@ -670,36 +659,24 @@ static int zynq_qspi_probe(struct platform_device *pd= ev) =20 init_completion(&xqspi->data_completion); =20 - xqspi->refclk =3D devm_clk_get(&pdev->dev, "ref_clk"); + xqspi->refclk =3D devm_clk_get_enabled(&pdev->dev, "ref_clk"); if (IS_ERR(xqspi->refclk)) { dev_err(&pdev->dev, "ref_clk clock not found.\n"); ret =3D PTR_ERR(xqspi->refclk); goto remove_ctlr; } =20 - ret =3D clk_prepare_enable(xqspi->pclk); - if (ret) { - dev_err(&pdev->dev, "Unable to enable APB clock.\n"); - goto remove_ctlr; - } - - ret =3D clk_prepare_enable(xqspi->refclk); - if (ret) { - dev_err(&pdev->dev, "Unable to enable device clock.\n"); - goto clk_dis_pclk; - } - xqspi->irq =3D platform_get_irq(pdev, 0); if (xqspi->irq < 0) { ret =3D xqspi->irq; - goto clk_dis_all; + goto remove_ctlr; } ret =3D devm_request_irq(&pdev->dev, xqspi->irq, zynq_qspi_irq, 0, pdev->name, xqspi); if (ret !=3D 0) { ret =3D -ENXIO; dev_err(&pdev->dev, "request_irq failed\n"); - goto clk_dis_all; + goto remove_ctlr; } =20 ret =3D of_property_read_u32(np, "num-cs", @@ -709,7 +686,7 @@ static int zynq_qspi_probe(struct platform_device *pdev) } else if (num_cs > ZYNQ_QSPI_MAX_NUM_CS) { ret =3D -EINVAL; dev_err(&pdev->dev, "only 2 chip selects are available\n"); - goto clk_dis_all; + goto remove_ctlr; } else { ctlr->num_chipselect =3D num_cs; } @@ -728,15 +705,11 @@ static int zynq_qspi_probe(struct platform_device *pd= ev) ret =3D devm_spi_register_controller(&pdev->dev, ctlr); if (ret) { dev_err(&pdev->dev, "devm_spi_register_controller failed\n"); - goto clk_dis_all; + goto remove_ctlr; } =20 return ret; =20 -clk_dis_all: - clk_disable_unprepare(xqspi->refclk); -clk_dis_pclk: - clk_disable_unprepare(xqspi->pclk); remove_ctlr: spi_controller_put(ctlr); =20 @@ -758,9 +731,6 @@ static void zynq_qspi_remove(struct platform_device *pd= ev) struct zynq_qspi *xqspi =3D platform_get_drvdata(pdev); =20 zynq_qspi_write(xqspi, ZYNQ_QSPI_ENABLE_OFFSET, 0); - - clk_disable_unprepare(xqspi->refclk); - clk_disable_unprepare(xqspi->pclk); } =20 static const struct of_device_id zynq_qspi_of_match[] =3D { --=20 2.25.1