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Tue, 9 Dec 2025 18:45:52 -0800 From: Nicolin Chen To: , , CC: , , , , , , Subject: [PATCH rc v3 4/4] iommu/arm-smmu-v3-test: Add nested s1bypass/s1dssbypass coverage Date: Tue, 9 Dec 2025 18:45:19 -0800 Message-ID: <229cbb478c40a031a0399d1037e07195139cdeba.1765334527.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A107:EE_|SJ1PR12MB6074:EE_ X-MS-Office365-Filtering-Correlation-Id: a322130d-5f53-4833-7c69-08de37963d5a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?3GWVB7/CTGo6Topi91k25n6ouEZM4i3+SPLhao9uYmK8myIamPW/fkBlkfMc?= =?us-ascii?Q?QFZepfO2Y61MI+dna4zJzCQC364DafXV2nKHxXUCt4MiZQCMuz/Qi4ePdsP7?= =?us-ascii?Q?+FfEVsgXtgA5wAUAnrtQydstfAq9+TDwkBD5PLsMMzVRcU8xe0YbQ7yuAiYg?= =?us-ascii?Q?y/7sG+ObT9VjLmX7TW/qTl5V43C0x5desKToJ9CEcyFmhcEQUZLnBCABEM1l?= =?us-ascii?Q?r9JSCNfiFTfMpH6CfdgGqA1OhsaCHqGs177ivH4HLQtml4DHyi3YsaMUNK3o?= =?us-ascii?Q?1j5T/TH9EzoqHlAEQLQv5WV50UhR1Rwh2kq6TUjmA/iEXZl81q2M9GEP9xpP?= =?us-ascii?Q?AZ1yE5fA8ymPZ9TEnOglJm/MKawNF0OuXqLMgk0XTdfn0UjQa0Vsg4uMIzBk?= =?us-ascii?Q?p2HI/Wwzd/ll3KwtMa9zxSJGqYtC6KxJd5VG9vOa3LAWr2eqffQaE/dMzPUJ?= =?us-ascii?Q?84H9QI6/mL/c0hEfurOSc5je7BRtTkZo3nvxkUCDwppvJ5m2Z7znzDf52El5?= =?us-ascii?Q?7oJgSYfG/xfOXWZSzi5xM1K/jq82let8EOM5PDv9Ej7ebhfgSLznCcJCDXBX?= =?us-ascii?Q?Z7iNlZGtPJPUhucg4t/A5npJbyHExFTe6TGXnL7eQm2OK41bmck6TWnMGFDx?= =?us-ascii?Q?5VaV0zSqo9Zai1CrAwk83v4IX4894d1wOUDTqGHPAbd9s5yYWjpCSu79DLuv?= =?us-ascii?Q?FmJZg5mZjyrfjbKFM83lxRwkfalMaQPufdlYKc5pKhutLpnHr5ehOxYET1AI?= =?us-ascii?Q?g5JpGZwtiKPnxwSy9ArFJbvETDcCxmx3DdyTyxxxWjDfvPCvcOjSs4TDWC8V?= =?us-ascii?Q?xC9Okm5jss/VPFKnsLFQEq1ujvTtxFrD5SwOwoUW38x5JS+I4fZSvJISbiZh?= =?us-ascii?Q?tIfuy4GUWtAoDU7pbBI6wzo0dh6WSNAS+mGjYPqUvkgdvS4atZGK620pvfcE?= =?us-ascii?Q?3zrExpTXYUUc4lspHydmrwt8I+2u9e3LbEmd0HsjZzuD3s+EOFH+3mNmV5aL?= =?us-ascii?Q?cxbvBjQaDaCYP4ONA9UqqkXO02Smfas85hVz8ejymYGfm+IDb/IQ+EDnYkCN?= =?us-ascii?Q?Qy98CeJssR7/aXJXUTL5fIM343KRxaPrKltvN4d4/R2E45Djo4m1PtLuNixX?= =?us-ascii?Q?qqEFiOalx0z6l16AonNeBSp32uIH3RddvbbTMWXMlmZYLNwktjpF/sYuMwJk?= =?us-ascii?Q?CggmMeixC5k53jnHOfJFOUaxGYTKHN6V5aOdJThI2FB0BMP/A8KuOu6AfHHf?= =?us-ascii?Q?ANkBdkJFcrSusUdQ2SsapM2RIEuaLJBbClBwxRhf2uEuwaX49yd4lFOkrhNy?= =?us-ascii?Q?hglW2ZGk/UBwQPRmokW2528hEXanerEqdTHD5I6c6Ml+ez7Vu2uXHmG670/w?= =?us-ascii?Q?GT5P9qh26IeAKfQMkh/ArCxAc3BJ+GVFEUhH4ccc/f4oI3o6+VXaUOF/UoGt?= =?us-ascii?Q?pvxTIuzqet+b+ft1vNKcMBWJ8+ew/gEEUdgOXvkoH3tkEFvA6gZMRYCEnGvC?= =?us-ascii?Q?SyF5jNDoVMdbR/+7ZLnGMK/CF9YuXVBm0TuHwVNEntfOxZt/jaSTksHYf2r9?= =?us-ascii?Q?iHSuuWbi6zjcviwztEk=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 02:45:54.5376 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a322130d-5f53-4833-7c69-08de37963d5a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A107.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6074 Content-Type: text/plain; charset="utf-8" STE in a nested case requires both S1 and S2 fields. And this makes the use case different from the existing one. Add coverage for previously failed cases shifting between S2-only and S1+S2 STEs. Reviewed-by: Shuai Xue Signed-off-by: Nicolin Chen --- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c b/drivers/iom= mu/arm/arm-smmu-v3/arm-smmu-v3-test.c index 3556e65cf9ac..ffa43e103692 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c @@ -33,8 +33,12 @@ static struct mm_struct sva_mm =3D { enum arm_smmu_test_master_feat { ARM_SMMU_MASTER_TEST_ATS =3D BIT(0), ARM_SMMU_MASTER_TEST_STALL =3D BIT(1), + ARM_SMMU_MASTER_TEST_NESTED =3D BIT(2), }; =20 +static void arm_smmu_test_make_s2_ste(struct arm_smmu_ste *ste, + enum arm_smmu_test_master_feat feat); + static bool arm_smmu_entry_differs_in_used_bits(const __le64 *entry, const __le64 *used_bits, const __le64 *target, @@ -198,6 +202,17 @@ static void arm_smmu_test_make_cdtable_ste(struct arm_= smmu_ste *ste, }; =20 arm_smmu_make_cdtable_ste(ste, &master, ats_enabled, s1dss); + if (feat & ARM_SMMU_MASTER_TEST_NESTED) { + struct arm_smmu_ste s2ste; + int i; + + arm_smmu_test_make_s2_ste(&s2ste, ARM_SMMU_MASTER_TEST_ATS); + ste->data[0] |=3D cpu_to_le64( + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_NESTED)); + ste->data[1] |=3D cpu_to_le64(STRTAB_STE_1_MEV); + for (i =3D 2; i < NUM_ENTRY_QWORDS; i++) + ste->data[i] =3D s2ste.data[i]; + } } =20 static void arm_smmu_v3_write_ste_test_bypass_to_abort(struct kunit *test) @@ -555,6 +570,35 @@ static void arm_smmu_v3_write_ste_test_s2_to_s1_stall(= struct kunit *test) NUM_EXPECTED_SYNCS(3)); } =20 +static void +arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + /* Expect an additional sync to unset ignored bits: EATS and MEV */ + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s1_ste, &s2_ste, + NUM_EXPECTED_SYNCS(3)); +} + +static void +arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass(struct kunit *te= st) +{ + struct arm_smmu_ste s1_ste; + struct arm_smmu_ste s2_ste; + + arm_smmu_test_make_cdtable_ste( + &s1_ste, STRTAB_STE_1_S1DSS_BYPASS, fake_cdtab_dma_addr, + ARM_SMMU_MASTER_TEST_ATS | ARM_SMMU_MASTER_TEST_NESTED); + arm_smmu_test_make_s2_ste(&s2_ste, 0); + arm_smmu_v3_test_ste_expect_hitless_transition(test, &s2_ste, &s1_ste, + NUM_EXPECTED_SYNCS(2)); +} + static void arm_smmu_v3_write_cd_test_sva_clear(struct kunit *test) { struct arm_smmu_cd cd =3D {}; @@ -601,6 +645,8 @@ static struct kunit_case arm_smmu_v3_test_cases[] =3D { KUNIT_CASE(arm_smmu_v3_write_cd_test_s1_change_asid), KUNIT_CASE(arm_smmu_v3_write_ste_test_s1_to_s2_stall), KUNIT_CASE(arm_smmu_v3_write_ste_test_s2_to_s1_stall), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1dssbypass_to_s1bypass), + KUNIT_CASE(arm_smmu_v3_write_ste_test_nested_s1bypass_to_s1dssbypass), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_clear), KUNIT_CASE(arm_smmu_v3_write_cd_test_sva_release), {}, --=20 2.43.0