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Fri, 25 Oct 2024 16:50:19 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 13/13] iommu/arm-smmu-v3: Add IOMMU_VIOMMU_TYPE_ARM_SMMUV3 support Date: Fri, 25 Oct 2024 16:49:53 -0700 Message-ID: <20c85597e5d579e020f027da4fc36275adcc91bf.1729897352.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023D1:EE_|SA1PR12MB7198:EE_ X-MS-Office365-Filtering-Correlation-Id: 9cb9b7f2-281c-47a7-73dc-08dcf54fd1f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Dp5pn2ykzMoaSgMhsxOi1e6GAFTPc4QBYIVN/9Nk4oR6j20qpaRDhopGYQyA?= =?us-ascii?Q?pgXW4qNUey9/QPR2KZNdcgyP3IHPqHozZE3T30fv1gQMl1u7lwXmpmLvdu8C?= =?us-ascii?Q?wgIU/O6yYGoGRk5Ax72rsysWPa1i0vhH+GzMjnesqyyphWI7APTTyn6giwyW?= =?us-ascii?Q?mJsy0ihfpKa6zvd1sJJcBg1BE1IBjPCh13u0h4qT6SeSczJUoPJl6Kkj1BF3?= =?us-ascii?Q?r5AOnjuNQdHYTbFI2jPohTuS23Vsta35ngFWYxbjbV96a7wQu4fxqySw+CnI?= =?us-ascii?Q?hZ3AOOWQhMOB0wtgvrJAQcJiccpYkLn2QgMF3osHhT1te3ZSMMkajNUaP0B5?= =?us-ascii?Q?WlkW3pVesmhwdmJzkzi/9psA09h0MO31fX3eaTLF/nulND+CiH2opx6DS3zl?= =?us-ascii?Q?cGtjB6+m7WHvQj+LcTUDXy12+2ICNRL1tAzkfn5GfkuQMuPTc2E3+D19Lgwv?= =?us-ascii?Q?7ZOI3K9dkZM60iqN0C+fRB2f8OzWarNwcGAfcM04rrLonqiZBcIVRZVlCwXS?= =?us-ascii?Q?vPuqRYBlUzhYuw+IrQo7daWnd5XlpCD28BucD9THgqFXSc3Kf+V0GW7AhYnx?= =?us-ascii?Q?LzprWa4o/0qgK/7KHdgw9ot96qlDae1fcH7ZMzi3bW5CGPMc0pbjofX/MDbk?= =?us-ascii?Q?yrq+KZrI3+wusXb0+fRkJrtfqrDymeDRvxW1HxydgkHqgwAIY8SFH9lGWp+W?= =?us-ascii?Q?I6h32ZoqToS5Kdu7Yv1iYmow2gzuqzP4hul2FcqHzbrRZdsgoT8s+L7nJwmb?= =?us-ascii?Q?S+HBSB3QvVRORZEjSevetIdCVilzo3tYOvcdgdvd1tQDyzU3NzvYK1Jy6flU?= =?us-ascii?Q?SzKYc1MIQK80p4/BseP1chiJ5duKmbdA/PxM6hsRE+3k1yT7aFOzbJdjdJxW?= =?us-ascii?Q?X7ItOhfwEfNSP/8X41hMSGhXcx47USo0AzBOCbwYGfNM2c514fJrvDYRRy2v?= =?us-ascii?Q?RBqNbn8UlW44kx0QxfK9VzrtnZ/4jg4Jds8UcCjVf08HqLngBXpm5FmEEa5s?= =?us-ascii?Q?Zifnm8Cs4Wol7YTgeg8OkpiSEG47joldB7OSh27gpC14cij2zTUQ0Js7wWVw?= =?us-ascii?Q?jvS3FT0c9n7MEDfaJ+dT8QBU4K62x+2NLSpUCiiI78pE+3BQfrA6JMepXcVv?= =?us-ascii?Q?0Dgjj+kOn0W3wtlZm3hZP3YBRQFpWlMra/BWen0j9p1oONJDvjit+Ayz3oa5?= =?us-ascii?Q?uLvbc3NZhonAnJRJjEaN4v0XD+POejhWz6PJpawniJRwumP0RbvYIFwYF5b0?= =?us-ascii?Q?BuUM66Ex3NSn7HO2/kMd1dnYfzhJFOAWlbSfMmkvZNoqVG5RtXRnr0I3GK5w?= =?us-ascii?Q?pTFysNLmXPiEEJP37ycaf6aeKs88eNWI9cZVTeLkRsF/Clfk1M6jDwGSnXoi?= =?us-ascii?Q?6aof0vo/r8i5+RWIPvYZKoYPhZb2OTdyKCoeVnkjG0e576vGIw=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 23:50:35.3029 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9cb9b7f2-281c-47a7-73dc-08dcf54fd1f0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D1.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7198 Content-Type: text/plain; charset="utf-8" Add a new driver-type for ARM SMMUv3 to enum iommu_viommu_type. Implement an arm_vsmmu_alloc() with its viommu op arm_vsmmu_domain_alloc_nested(), to replace arm_smmu_domain_alloc_nesting(). As an initial step, copy the VMID from s2_parent. A later cleanup series is required to move the VMID allocation out of the stage-2 domain allocation routine to this. After that, replace nested_domain->s2_parent with nested_domain->vsmmu. Note that the validatting conditions for a nested_domain allocation are moved from arm_vsmmu_domain_alloc_nested to arm_vsmmu_alloc, since there is no point in creating a vIOMMU (vsmmu) from the beginning if it would not support a nested_domain. Signed-off-by: Nicolin Chen Reviewed-by: Kevin Tian --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 26 +++--- include/uapi/linux/iommufd.h | 2 + .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 80 ++++++++++++------- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 +-- 4 files changed, 71 insertions(+), 46 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 956c12637866..5a025d310dbe 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -10,6 +10,7 @@ =20 #include #include +#include #include #include #include @@ -835,7 +836,7 @@ struct arm_smmu_domain { =20 struct arm_smmu_nested_domain { struct iommu_domain domain; - struct arm_smmu_domain *s2_parent; + struct arm_vsmmu *vsmmu; =20 __le64 ste[2]; }; @@ -1005,21 +1006,22 @@ tegra241_cmdqv_probe(struct arm_smmu_device *smmu) } #endif /* CONFIG_TEGRA241_CMDQV */ =20 +struct arm_vsmmu { + struct iommufd_viommu core; + struct arm_smmu_device *smmu; + struct arm_smmu_domain *s2_parent; + u16 vmid; +}; + #if IS_ENABLED(CONFIG_ARM_SMMU_V3_IOMMUFD) void *arm_smmu_hw_info(struct device *dev, u32 *length, u32 *type); -struct iommu_domain * -arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, - struct iommu_domain *parent, - const struct iommu_user_data *user_data); +struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, + struct iommu_domain *parent, + struct iommufd_ctx *ictx, + unsigned int viommu_type); #else #define arm_smmu_hw_info NULL -static inline struct iommu_domain * -arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, - struct iommu_domain *parent, - const struct iommu_user_data *user_data) -{ - return ERR_PTR(-EOPNOTSUPP); -} +#define arm_vsmmu_alloc NULL #endif /* CONFIG_ARM_SMMU_V3_IOMMUFD */ =20 #endif /* _ARM_SMMU_V3_H */ diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 717659b9fdce..56c742106a45 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -859,9 +859,11 @@ struct iommu_fault_alloc { /** * enum iommu_viommu_type - Virtual IOMMU Type * @IOMMU_VIOMMU_TYPE_DEFAULT: Reserved for future use + * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT =3D 0, + IOMMU_VIOMMU_TYPE_ARM_SMMUV3 =3D 1, }; =20 /** diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 44e1b9bef850..abb6d2868376 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -34,7 +34,8 @@ static void arm_smmu_make_nested_cd_table_ste( struct arm_smmu_ste *target, struct arm_smmu_master *master, struct arm_smmu_nested_domain *nested_domain, bool ats_enabled) { - arm_smmu_make_s2_domain_ste(target, master, nested_domain->s2_parent, + arm_smmu_make_s2_domain_ste(target, master, + nested_domain->vsmmu->s2_parent, ats_enabled); =20 target->data[0] =3D cpu_to_le64(STRTAB_STE_0_V | @@ -75,7 +76,8 @@ static void arm_smmu_make_nested_domain_ste( break; case STRTAB_STE_0_CFG_BYPASS: arm_smmu_make_s2_domain_ste( - target, master, nested_domain->s2_parent, ats_enabled); + target, master, nested_domain->vsmmu->s2_parent, + ats_enabled); break; case STRTAB_STE_0_CFG_ABORT: default: @@ -100,7 +102,7 @@ static int arm_smmu_attach_dev_nested(struct iommu_doma= in *domain, struct arm_smmu_ste ste; int ret; =20 - if (nested_domain->s2_parent->smmu !=3D master->smmu) + if (nested_domain->vsmmu->smmu !=3D master->smmu) return -EINVAL; if (arm_smmu_ssids_in_use(&master->cd_table)) return -EBUSY; @@ -151,36 +153,15 @@ static int arm_smmu_validate_vste(struct iommu_hwpt_a= rm_smmuv3 *arg) return 0; } =20 -struct iommu_domain * -arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, - struct iommu_domain *parent, +static struct iommu_domain * +arm_vsmmu_alloc_domain_nested(struct iommufd_viommu *viommu, const struct iommu_user_data *user_data) { - struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + struct arm_vsmmu *vsmmu =3D container_of(viommu, struct arm_vsmmu, core); struct arm_smmu_nested_domain *nested_domain; - struct arm_smmu_domain *smmu_parent; struct iommu_hwpt_arm_smmuv3 arg; int ret; =20 - if (flags || !(master->smmu->features & ARM_SMMU_FEAT_NESTING)) - return ERR_PTR(-EOPNOTSUPP); - - /* - * Must support some way to prevent the VM from bypassing the cache - * because VFIO currently does not do any cache maintenance. - */ - if (!arm_smmu_master_canwbs(master) && - !(master->smmu->features & ARM_SMMU_FEAT_S2FWB)) - return ERR_PTR(-EOPNOTSUPP); - - /* - * The core code checks that parent was created with - * IOMMU_HWPT_ALLOC_NEST_PARENT - */ - smmu_parent =3D to_smmu_domain(parent); - if (smmu_parent->smmu !=3D master->smmu) - return ERR_PTR(-EINVAL); - ret =3D iommu_copy_struct_from_user(&arg, user_data, IOMMU_HWPT_DATA_ARM_SMMUV3, ste); if (ret) @@ -196,9 +177,52 @@ arm_smmu_domain_alloc_nesting(struct device *dev, u32 = flags, =20 nested_domain->domain.type =3D IOMMU_DOMAIN_NESTED; nested_domain->domain.ops =3D &arm_smmu_nested_ops; - nested_domain->s2_parent =3D smmu_parent; + nested_domain->vsmmu =3D vsmmu; nested_domain->ste[0] =3D arg.ste[0]; nested_domain->ste[1] =3D arg.ste[1] & ~cpu_to_le64(STRTAB_STE_1_EATS); =20 return &nested_domain->domain; } + + +static const struct iommufd_viommu_ops arm_vsmmu_ops =3D { + .alloc_domain_nested =3D arm_vsmmu_alloc_domain_nested, +}; + +struct iommufd_viommu *arm_vsmmu_alloc(struct device *dev, + struct iommu_domain *parent, + struct iommufd_ctx *ictx, + unsigned int viommu_type) +{ + struct arm_smmu_device *smmu =3D + iommu_get_iommu_dev(dev, struct arm_smmu_device, iommu); + struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + struct arm_smmu_domain *s2_parent =3D to_smmu_domain(parent); + struct arm_vsmmu *vsmmu; + + if (viommu_type !=3D IOMMU_VIOMMU_TYPE_ARM_SMMUV3) + return ERR_PTR(-EOPNOTSUPP); + + if (!(smmu->features & ARM_SMMU_FEAT_NESTING)) + return ERR_PTR(-EOPNOTSUPP); + + /* + * Must support some way to prevent the VM from bypassing the cache + * because VFIO currently does not do any cache maintenance. + */ + if (!arm_smmu_master_canwbs(master) && + !(smmu->features & ARM_SMMU_FEAT_S2FWB)) + return ERR_PTR(-EOPNOTSUPP); + + vsmmu =3D iommufd_viommu_alloc(ictx, struct arm_vsmmu, core, + &arm_vsmmu_ops); + if (IS_ERR(vsmmu)) + return ERR_CAST(vsmmu); + + vsmmu->smmu =3D smmu; + vsmmu->s2_parent =3D s2_parent; + /* FIXME Move VMID allocation from the S2 domain allocation to here */ + vsmmu->vmid =3D s2_parent->s2_cfg.vmid; + + return &vsmmu->core; +} diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.c index 0d79a1bd9049..8215c49d3bac 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2661,7 +2661,7 @@ to_smmu_domain_devices(struct iommu_domain *domain) domain->type =3D=3D IOMMU_DOMAIN_SVA) return to_smmu_domain(domain); if (domain->type =3D=3D IOMMU_DOMAIN_NESTED) - return to_smmu_nested_domain(domain)->s2_parent; + return to_smmu_nested_domain(domain)->vsmmu->s2_parent; return NULL; } =20 @@ -3126,13 +3126,9 @@ arm_smmu_domain_alloc_user(struct device *dev, u32 f= lags, struct arm_smmu_domain *smmu_domain; int ret; =20 - if (parent) - return arm_smmu_domain_alloc_nesting(dev, flags, parent, - user_data); - if (flags & ~PAGING_FLAGS) return ERR_PTR(-EOPNOTSUPP); - if (user_data) + if (parent || user_data) return ERR_PTR(-EOPNOTSUPP); =20 smmu_domain =3D arm_smmu_domain_alloc(); @@ -3541,6 +3537,7 @@ static struct iommu_ops arm_smmu_ops =3D { .dev_disable_feat =3D arm_smmu_dev_disable_feature, .page_response =3D arm_smmu_page_response, .def_domain_type =3D arm_smmu_def_domain_type, + .viommu_alloc =3D arm_vsmmu_alloc, .user_pasid_table =3D 1, .pgsize_bitmap =3D -1UL, /* Restricted during device attach */ .owner =3D THIS_MODULE, --=20 2.43.0