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Fri, 21 Mar 2025 07:36:21 -0700 (PDT) Received: from localhost ([196.207.164.177]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-43d4fd277d5sm28710235e9.19.2025.03.21.07.36.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Mar 2025 07:36:20 -0700 (PDT) Date: Fri, 21 Mar 2025 17:36:18 +0300 From: Dan Carpenter To: Lubomir Rintel Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sam Ravnborg , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH] drm/bridge: chrontel-ch7033: Fix precedence bug in ch7033_bridge_mode_set() Message-ID: <20c0422d-b4fc-4ec7-b3e5-4c4679f499f5@stanley.mountain> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline X-Mailer: git-send-email haha only kidding Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The problem is that the bitwise OR operation has higher precedence than the ternary expression. The existing code will either set HPO_I, VPO_I, or "mode->clock >> 16" but not a combination of the three which is what we want. Fixes: e7f12054a1b9 ("drm/bridge: chrontel-ch7033: Add a new driver") Signed-off-by: Dan Carpenter --- From static analysis. Not tested! drivers/gpu/drm/bridge/chrontel-ch7033.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/bridge/chrontel-ch7033.c b/drivers/gpu/drm/bri= dge/chrontel-ch7033.c index da17f0978a79..1b858a8ced57 100644 --- a/drivers/gpu/drm/bridge/chrontel-ch7033.c +++ b/drivers/gpu/drm/bridge/chrontel-ch7033.c @@ -404,9 +404,9 @@ static void ch7033_bridge_mode_set(struct drm_bridge *b= ridge, /* Input clock and sync polarity. */ regmap_update_bits(priv->regmap, 0x19, 0x1, mode->clock >> 16); regmap_update_bits(priv->regmap, 0x19, HPO_I | VPO_I | GCLKFREQ, - (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0 | - (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0 | - mode->clock >> 16); + ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_I : 0) | + ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_I : 0) | + (mode->clock >> 16)); regmap_write(priv->regmap, 0x1a, mode->clock >> 8); regmap_write(priv->regmap, 0x1b, mode->clock); =20 @@ -427,8 +427,8 @@ static void ch7033_bridge_mode_set(struct drm_bridge *b= ridge, =20 /* Output sync polarity. */ regmap_update_bits(priv->regmap, 0x2e, HPO_O | VPO_O, - (mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0 | - (mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0); + ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? HPO_O : 0) | + ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? VPO_O : 0)); =20 /* HDMI horizontal output timing. */ regmap_update_bits(priv->regmap, 0x54, HWO_HDMI_HI | HOO_HDMI_HI, --=20 2.47.2