From nobody Sun Apr 5 19:42:17 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA91137FF5D for ; Wed, 1 Apr 2026 04:57:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019471; cv=none; b=oRIyNpWL+I8zv3XbnFlJGEK/UfajI5vd1wcCCvv8A6WakwYkNZQ2fGkkMKDWA5oePdj0xhSBsqkBKR2GaWPCDlGpwoRPx+ja99GDBDZZqPfv/edAUmvd4Hsbz1eruaxC2gfPuOzy04tX0ZFO9EbBftEyCE/Vd70IMaYpzXWDzH8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019471; c=relaxed/simple; bh=YsqalQAe/OCRyIHlLpgRRfoU/NRoj+H/1pjvmU21LAE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FQ3FQfle+Mdnm1/YGk4L0S5pabyVXMLEFeiP4YRM4uU9/RPJrSDnziPw0ezWxkFtNJuK9qDVRyZMuTJ40gz++yXtCNn9DUaERqQmEcP2RABjjuq5QHHkXbQrZwbN+uad8OegPosR3n/XZkjF6grLuKYaEU1uFE2TDkkxvQ2jRMk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TL0rP4AL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TL0rP4AL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE19CC4CEF7; Wed, 1 Apr 2026 04:57:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775019471; bh=YsqalQAe/OCRyIHlLpgRRfoU/NRoj+H/1pjvmU21LAE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TL0rP4ALr0t+OfYFClnEht4ZjeaXZXNBzlJIwBgAU/PSpfFRO0CGI1RjrcFmLvVC6 Dm7mF5C3CSBY7Boq+qre0EE5C3+gyrhkQ+EUHc53kroSDZcsxep6e3X/Msyuhbqd9w jxmWUS3IAkcdL6IAPQ2mB74zwktl/7o88s6RbQLRMLZQ0J3VA4LVtGAp7JlVtpqPtk a0Hd+9gci0ZSpNiNHTcV9XHRnprgpXTdcFw/lOVoHzLxM042VwDGY8qbUqbh0lABrs fVQrhnfxM9RCuk0ndOKJfYm5bVsKq2Wzo6q5mxf1QxeupBcsJ6uamcXBtHcnLvUSUa 0s8KQhwSwbX9A== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao Subject: [PATCH 3/5] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Wed, 1 Apr 2026 10:26:34 +0530 Message-ID: <2086bdb889d265e5da5b48b61580fe4b7db340ee.1775019269.git.naveen@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index e0bd5051db2a..61d14cbdda49 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1838,13 +1838,13 @@ static void force_ibs_eilvt_setup(void) =20 preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset =3D 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset =3D 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); =20 - if (offset =3D=3D APIC_EILVT_NR_MAX) { + if (offset =3D=3D APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } --=20 2.53.0