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Thu, 26 Jun 2025 12:35:38 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v7 23/28] iommu/arm-smmu-v3-iommufd: Add hw_info to impl_ops Date: Thu, 26 Jun 2025 12:34:54 -0700 Message-ID: <205f234c05d6b09de52124a72a6978b74d832cfb.1750966133.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000206:EE_|PH7PR12MB8177:EE_ X-MS-Office365-Filtering-Correlation-Id: a492234e-e7f2-4259-b735-08ddb4e8ad19 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?uU1A/1iz7xcREEsKwD2myGF0fWyogMaG7RdndZ8Yj+YcRLTmKxuAWZpIXYBw?= =?us-ascii?Q?2zBpDCID0rYwwDHCXl7r3S8K0/V7cuM4dm3q/idAuZiEIN2cm3yZi6CWUSad?= =?us-ascii?Q?nCrsGxyxrtS8QZ/KpNDQ84G3OO9dtEeGUhU5Xcm1AC882pd/i5TW2XOupA/C?= =?us-ascii?Q?bn0C66QE3f8UW1ka8J5SM//fn/MjOhV3zzjX84/BY2RWEuVpky+H3jhvUSCe?= =?us-ascii?Q?/T2EeUNhGni3izJGcGD5jtnpq6jAW6usXvLU16Sfx8DtWD/ogQXwWqMK9PF0?= =?us-ascii?Q?ODpFR5RWABDLVYDvegztHheKRuAqrZNOtgwtMtIorx5ESxq5RVjHps8e27Sn?= =?us-ascii?Q?NLWxjnuJb0r4ab+jWRIC1Cw7NhbSoa8t9PO+OqXa3vP2wFEMGRqpllrKeuhk?= =?us-ascii?Q?Ckrokl7Uh9pwLSErwIOKgr3yz5Ydi6leaoUvj8ZObAD8fg62oGSnQavU9O9B?= =?us-ascii?Q?owHTbpMa4yz8zJYcQc862Rc0387ljRJhc/S1bjrzijLk3yWl6YRjtsIX0XkL?= =?us-ascii?Q?tl2fPdFtRwSqh1Gn4fn104v7AdwRxeEJRWpxzUv1+SqONvFG5bNyDyakY4Ti?= =?us-ascii?Q?o3rgVfPerHN9jht+Nd+csyFVkKWO5lWBEAJ0CZG4iC4MoPYk+wg6nffGVC+0?= =?us-ascii?Q?etJZQwm/uxXaD/MJK20fZAXjxAYu1EAizzybdv7OiXhaJ8gNsx7/kQ9qj1oz?= =?us-ascii?Q?51JX5h1YbUMZEhXGoVJI6UWbDrzu6UU8SU/la8F/tAeTTBkHFuLBWEVWAWlE?= =?us-ascii?Q?ETDiV8ctsvux9V51dKC0WMTO5dU/4oQP36QyiqhEYjq6WkEPpEfj7THiH/lF?= =?us-ascii?Q?1cBuy3KWrr3DkH+SSGXfudHYDIMBjSYylVa57pNzmIYmUSF+92hX9BxFS5er?= =?us-ascii?Q?gCzRWv/8XIkIyNbhlWzi9xd+u9tb6BAm52u9tLabKnK+hLja1I+zYreE/Nr0?= =?us-ascii?Q?Vow6Dk9/B6ORRVD3Lq42wf6EmHxazgoo6zg0S+7qPn9SDWiEUjGjYERRR68F?= =?us-ascii?Q?1OcqTP0ZT4ojtOSGxsaTVkbKk20CbwsyUJ+hl8gOoOq80APF5j2+Urv2hof4?= =?us-ascii?Q?qc1gIKGdtPhV/ymv414qgdeKVCSer3TIv3EZE/l1z9nuBiQwISImal/VhAtx?= =?us-ascii?Q?9POe85k6ZSlc7Fi8aHLPNIuApFXWX1mK2oGbdmaz7es+ehbE0C4gssPW6OqI?= =?us-ascii?Q?iCG/jWSg54jYgQDwf8art3zwTacvYIi4ryUL8FN+TQyh9SGuQgnYRUTUzFwm?= =?us-ascii?Q?eNmYRe4sq+8lxEW4b8gXpNOrYNsaXkzSX/NvOSSljL9Bkt0MZguby7lnGno5?= =?us-ascii?Q?pEU3XW/8kCqgaT7eVngUZtxeKc7RLzXSbDe1LrY74s8q4tsp+yI+fHE2M1LL?= =?us-ascii?Q?OD/HmRd1u9aIxRtauqUyyAJ1PprgRd5tgbGErssGZ5m0exlaL3C3KmxhQRi2?= =?us-ascii?Q?p40RLF9pAzScBfw0mUKlT66EBnAlOuAEEezeo6wQT+VLFh+v5CROY6RYkraC?= =?us-ascii?Q?n/xEdPfmrSh9nhJwohWymm71qn41MRm1iFsf?= X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jun 2025 19:35:58.5738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a492234e-e7f2-4259-b735-08ddb4e8ad19 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000206.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8177 Content-Type: text/plain; charset="utf-8" This will be used by Tegra241 CMDQV implementation to report a non-default HW info data. Reviewed-by: Jason Gunthorpe Signed-off-by: Nicolin Chen Reviewed-by: Pranjal Shrivastava --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 7 +++++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 8 ++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/ar= m/arm-smmu-v3/arm-smmu-v3.h index 07589350b2a1..836d5556008e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -721,6 +721,13 @@ struct arm_smmu_impl_ops { int (*init_structures)(struct arm_smmu_device *smmu); struct arm_smmu_cmdq *(*get_secondary_cmdq)( struct arm_smmu_device *smmu, struct arm_smmu_cmdq_ent *ent); + /* + * An implementation should define its own type other than the default + * IOMMU_HW_INFO_TYPE_ARM_SMMUV3. And it must validate the input @type + * to return its own structure. + */ + void *(*hw_info)(struct arm_smmu_device *smmu, u32 *length, + enum iommu_hw_info_type *type); const size_t vsmmu_size; const enum iommu_viommu_type vsmmu_type; int (*vsmmu_init)(struct arm_vsmmu *vsmmu, diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c b/drivers/= iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c index 2ab1c6cf4aac..1cf9646e776f 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-iommufd.c @@ -11,13 +11,17 @@ void *arm_smmu_hw_info(struct device *dev, u32 *length, enum iommu_hw_info_type *type) { struct arm_smmu_master *master =3D dev_iommu_priv_get(dev); + const struct arm_smmu_impl_ops *impl_ops =3D master->smmu->impl_ops; struct iommu_hw_info_arm_smmuv3 *info; u32 __iomem *base_idr; unsigned int i; =20 if (*type !=3D IOMMU_HW_INFO_TYPE_DEFAULT && - *type !=3D IOMMU_HW_INFO_TYPE_ARM_SMMUV3) - return ERR_PTR(-EOPNOTSUPP); + *type !=3D IOMMU_HW_INFO_TYPE_ARM_SMMUV3) { + if (!impl_ops || !impl_ops->hw_info) + return ERR_PTR(-EOPNOTSUPP); + return impl_ops->hw_info(master->smmu, length, type); + } =20 info =3D kzalloc(sizeof(*info), GFP_KERNEL); if (!info) --=20 2.43.0