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charset="utf-8" From: Shengjiu Wang The HiFi4 DSP provides a separate reset control for its debug logic. Keep this reset deasserted so that an external debug agent can access the DSP and perform debug operations. Also require the reset properties for the i.MX8ULP HiFi4 DSP. Signed-off-by: Shengjiu Wang --- Documentation/devicetree/bindings/dsp/fsl,dsp.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documenta= tion/devicetree/bindings/dsp/fsl,dsp.yaml index e610b7636a08..2f4c8623ff21 100644 --- a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml @@ -84,12 +84,14 @@ properties: =20 resets: minItems: 1 + maxItems: 3 =20 reset-names: minItems: 1 items: - const: runstall - const: softreset + - const: dbgreset =20 access-controllers: maxItems: 1 @@ -183,6 +185,8 @@ allOf: enum: - fsl,imx8mp-dsp - fsl,imx8mp-hifi4 + - fsl,imx8ulp-dsp + - fsl,imx8ulp-hifi4 then: required: - resets --=20 2.34.1 From nobody Thu Nov 5 05:42:02 2026 Authentication-Results: smtp.subspace.kernel.org; arc=pass header.oldest-pass=0 smtp.remote-ip=40.107.159.56 ARC-Seal: i=2; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=pass; t=1793846294; b=ND1QpJllc7Z9lDrKDi47z7wrqm5+zdx+iFA8r6VfubEks13bO7Y0blv5bf6jvkWYaJ+I +vH6antWrFc0qHsXGs3VlnxL4XjGFRdHWyEGbxBHsB+3Dt5y0y9Ks4j53DPkguyqR3//o MgtB+NlYR+zYzP1hOJLUQfWc9WFeNl0Qkru2KHwFI37OSHMLGGHQTBoqvJmH7Dyodutvt avOJR0/DtvdryRl1PGKV9TiKpZyJxZaGAxOSseWCP4ksvKcx2eNNSwL3A5w1QA7IfYYaj Z9hDV/B3YSLWjdatVHNtVteWiq+AgGrQZ4GqtlHi/xpbcnlx/jLQELDT8nd/P1b8Z8w== ARC-Message-Signature: i=2; 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charset="utf-8" From: Shengjiu Wang Add soft_rst and dbg_rst to struct imx_dsp_rproc for the softreset and dbgreset controls defined in the DSP binding. Update imx_dsp_rproc_reset_ctrl_detect_mode() to acquire the runstall, softreset, and dbgreset controls. The softreset and dbgreset controls are optional. Rewrite imx8ulp_dsp_reset() to use the reset controller API instead of accessing the reset registers directly. This relies on the i.MX8ULP SIM LPAV reset controller support added by commit 5aac7afc752b ("reset: imx8mp-audiomix: Support i.MX8ULP SIM LPAV"). The imx_dsp_rproc_mmio_*() helpers are no longer needed after this change, so remove them. Signed-off-by: Shengjiu Wang --- drivers/remoteproc/imx_dsp_rproc.c | 76 +++++++++--------------------- 1 file changed, 21 insertions(+), 55 deletions(-) diff --git a/drivers/remoteproc/imx_dsp_rproc.c b/drivers/remoteproc/imx_ds= p_rproc.c index 96d619daf3f5..0b0042525ea2 100644 --- a/drivers/remoteproc/imx_dsp_rproc.c +++ b/drivers/remoteproc/imx_dsp_rproc.c @@ -108,8 +108,9 @@ enum imx_dsp_rp_mbox_messages { =20 /** * struct imx_dsp_rproc - DSP remote processor state - * @regmap: regmap handler * @run_stall: reset control handle used for Run/Stall operation + * @soft_rst: reset control handle used for DSP core reset + * @dbg_rst: reset control handle used for DSP debug logic * @rproc: rproc handler * @dsp_dcfg: device configuration pointer * @clks: clocks needed by this device @@ -125,8 +126,9 @@ enum imx_dsp_rp_mbox_messages { * @flags: control flags */ struct imx_dsp_rproc { - struct regmap *regmap; struct reset_control *run_stall; + struct reset_control *soft_rst; + struct reset_control *dbg_rst; struct rproc *rproc; const struct imx_dsp_rproc_dcfg *dsp_dcfg; struct clk_bulk_data clks[DSP_RPROC_CLK_MAX]; @@ -243,20 +245,15 @@ static int imx8ulp_dsp_reset(struct imx_dsp_rproc *pr= iv) struct arm_smccc_res res; =20 /* Put DSP into reset and stall */ - regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, - IMX8ULP_SYSCTRL0_DSP_RST, IMX8ULP_SYSCTRL0_DSP_RST); - regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, - IMX8ULP_SYSCTRL0_DSP_STALL, - IMX8ULP_SYSCTRL0_DSP_STALL); + reset_control_assert(priv->soft_rst); + reset_control_assert(priv->run_stall); =20 /* Configure resources of DSP through TFA */ arm_smccc_smc(IMX8ULP_SIP_HIFI_XRDC, 0, 0, 0, 0, 0, 0, 0, &res); =20 /* Take the DSP out of reset and keep stalled for FW loading */ - regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, - IMX8ULP_SYSCTRL0_DSP_RST, 0); - regmap_update_bits(priv->regmap, IMX8ULP_SIM_LPAV_REG_SYSCTRL0, - IMX8ULP_SYSCTRL0_DSP_DBG_RST, 0); + reset_control_deassert(priv->soft_rst); + reset_control_deassert(priv->dbg_rst); =20 return 0; } @@ -338,14 +335,6 @@ static int imx_dsp_rproc_handle_rsc(struct rproc *rpro= c, u32 rsc_type, return RSC_HANDLED; } =20 -static int imx_dsp_rproc_mmio_start(struct rproc *rproc) -{ - struct imx_dsp_rproc *priv =3D rproc->priv; - const struct imx_rproc_dcfg *dcfg =3D priv->dsp_dcfg->dcfg; - - return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dc= fg->src_start); -} - static int imx_dsp_rproc_reset_ctrl_start(struct rproc *rproc) { struct imx_dsp_rproc *priv =3D rproc->priv; @@ -391,14 +380,6 @@ static int imx_dsp_rproc_start(struct rproc *rproc) return 0; } =20 -static int imx_dsp_rproc_mmio_stop(struct rproc *rproc) -{ - struct imx_dsp_rproc *priv =3D rproc->priv; - const struct imx_rproc_dcfg *dcfg =3D priv->dsp_dcfg->dcfg; - - return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dc= fg->src_stop); -} - static int imx_dsp_rproc_reset_ctrl_stop(struct rproc *rproc) { struct imx_dsp_rproc *priv =3D rproc->priv; @@ -1024,23 +1005,6 @@ static int imx_dsp_attach_pm_domains(struct imx_dsp_= rproc *priv) return devm_pm_domain_attach_list(dev, NULL, &priv->pd_list); } =20 -static int imx_dsp_rproc_mmio_detect_mode(struct rproc *rproc) -{ - struct imx_dsp_rproc *priv =3D rproc->priv; - struct device *dev =3D rproc->dev.parent; - struct regmap *regmap; - - regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,dsp-ctrl"); - if (IS_ERR(regmap)) { - dev_err(dev, "failed to find syscon\n"); - return PTR_ERR(regmap); - } - - priv->regmap =3D regmap; - - return 0; -} - static int imx_dsp_rproc_reset_ctrl_detect_mode(struct rproc *rproc) { struct imx_dsp_rproc *priv =3D rproc->priv; @@ -1052,6 +1016,18 @@ static int imx_dsp_rproc_reset_ctrl_detect_mode(stru= ct rproc *rproc) return PTR_ERR(priv->run_stall); } =20 + priv->soft_rst =3D devm_reset_control_get_optional_exclusive(dev, "softre= set"); + if (IS_ERR(priv->soft_rst)) { + dev_err(dev, "Failed to get DSP soft reset control\n"); + return PTR_ERR(priv->soft_rst); + } + + priv->dbg_rst =3D devm_reset_control_get_optional_exclusive(dev, "dbgrese= t"); + if (IS_ERR(priv->dbg_rst)) { + dev_err(dev, "Failed to get DSP debug reset control\n"); + return PTR_ERR(priv->dbg_rst); + } + return 0; } =20 @@ -1316,12 +1292,6 @@ static const struct dev_pm_ops imx_dsp_rproc_pm_ops = =3D { RUNTIME_PM_OPS(imx_dsp_runtime_suspend, imx_dsp_runtime_resume, NULL) }; =20 -static const struct imx_rproc_plat_ops imx_dsp_rproc_ops_mmio =3D { - .start =3D imx_dsp_rproc_mmio_start, - .stop =3D imx_dsp_rproc_mmio_stop, - .detect_mode =3D imx_dsp_rproc_mmio_detect_mode, -}; - static const struct imx_rproc_plat_ops imx_dsp_rproc_ops_reset_ctrl =3D { .start =3D imx_dsp_rproc_reset_ctrl_start, .stop =3D imx_dsp_rproc_reset_ctrl_stop, @@ -1348,13 +1318,9 @@ static const struct imx_dsp_rproc_dcfg imx_dsp_rproc= _cfg_imx8mp =3D { =20 /* Specific configuration for i.MX8ULP */ static const struct imx_rproc_dcfg dsp_rproc_cfg_imx8ulp =3D { - .src_reg =3D IMX8ULP_SIM_LPAV_REG_SYSCTRL0, - .src_mask =3D IMX8ULP_SYSCTRL0_DSP_STALL, - .src_start =3D 0, - .src_stop =3D IMX8ULP_SYSCTRL0_DSP_STALL, .att =3D imx_dsp_rproc_att_imx8ulp, .att_size =3D ARRAY_SIZE(imx_dsp_rproc_att_imx8ulp), - .ops =3D &imx_dsp_rproc_ops_mmio, + .ops =3D &imx_dsp_rproc_ops_reset_ctrl, }; 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charset="utf-8" From: Shengjiu Wang Add the HiFi4 DSP node with the required registers, clocks, firmware reference, and mailbox connections. Keep the node disabled by default, allowing boards to enable it when HiFi4 DSP support is needed. Signed-off-by: Shengjiu Wang --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8ulp.dtsi index ac8293f81c6b..6d8dccaf8ac3 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include =20 #include "imx8ulp-pinfunc.h" @@ -208,6 +209,28 @@ soc: soc@0 { ranges =3D <0x0 0x0 0x0 0x40000000>, <0x60000000 0x0 0x60000000 0x1000000>; =20 + dsp: dsp@21170000 { + compatible =3D "fsl,imx8ulp-hifi4"; + reg =3D <0x21170000 0x20000>; + clocks =3D <&sim_lpav IMX8ULP_CLK_SIM_LPAV_HIFI_PBCLK>, + <&sim_lpav IMX8ULP_CLK_SIM_LPAV_HIFI_PLAT>, + <&sim_lpav IMX8ULP_CLK_SIM_LPAV_HIFI_CORE>, + <&cgc1 IMX8ULP_CLK_DUMMY>, + <&pcc5 IMX8ULP_CLK_MU3_B>; + clock-names =3D "ipg", "ocram", "core", "debug", "mu"; + firmware-name =3D "imx/dsp/hifi4.bin"; + mboxes =3D <&mu3 0 0>, + <&mu3 1 0>, + <&mu3 3 0>; + mbox-names =3D "tx", "rx", "rxdb"; + power-domains =3D <&scmi_devpd IMX8ULP_PD_HIFI4>; + resets =3D <&sim_lpav IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL>, + <&sim_lpav IMX8ULP_SIM_LPAV_HIFI4_DSP_RST>, + <&sim_lpav IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST>; + reset-names =3D "runstall", "softreset", "dbgreset"; + status =3D "disabled"; + }; + s4muap: mailbox@27020000 { compatible =3D "fsl,imx8ulp-mu-s4"; reg =3D <0x27020000 0x10000>; --=20 2.34.1 From nobody Thu Nov 5 05:42:02 2026 Authentication-Results: smtp.subspace.kernel.org; arc=pass header.oldest-pass=0 smtp.remote-ip=52.101.72.15 ARC-Seal: i=2; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=pass; t=1793846306; b=GE5FugUYw0GWKBsX6GsU4VuQpr8LLgYDYpmDP1oShFWbeLUBN06PHvePtXtiabD3XcjD ySdfcXnHVm0w/wA3S8PHJe01nxbmwBKyT5qQ40IcxHINTF6xsVIOuyhm5KQJI+B9QBjZI t13j5a6BklNfLrEWt+j5UCStbgjHO60vED69u2Hb+N2n9C2A8PcrsCohaqWm2BfI6N1p8 Ssht2FfwIgVFkU8KnLaYFFFhBWnmm5fw12nEbCbA+O+pN6/19yyMXjoEBwZGE7OSZNrm6 U4Q+lZH7X1z8FnYtcVw/sfvWAcdpaA/Z0rVQxFHTiCAVbZ1xJMtBOTOAvdKQU4L1Fag== ARC-Message-Signature: i=2; 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charset="utf-8" From: Shengjiu Wang Configure the HiFi4 DSP clocks and memory regions, including the vdev0vring0, vdev0vring1, vdev0buffer, and dsp_reserved regions. Enable MU3, which provides the mailbox used for communication with the DSP, and enable the HiFi4 DSP. Signed-off-by: Shengjiu Wang --- arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boo= t/dts/freescale/imx8ulp-evk.dts index fdf3aab2224b..f985a9e7010d 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts @@ -61,6 +61,27 @@ rsc_table: rsc-table@20000000 { no-map; }; =20 + dsp_reserved: memory@8e000000 { + reg =3D <0 0x8e000000 0 0x1000000>; + no-map; + }; + + dsp_vdev0vring0: vdev0vring0@8fef0000 { + reg =3D <0 0x8fef0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: vdev0vring1@8fef8000 { + reg =3D <0 0x8fef8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: vdev0buffer@8ff00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x8ff00000 0 0x100000>; + no-map; + }; + vdev0vring0: vdev0vring0@aff00000 { reg =3D <0 0xaff00000 0 0x8000>; no-map; @@ -145,6 +166,15 @@ &cm33 { status =3D "okay"; }; =20 +&dsp { + assigned-clocks =3D <&cgc2 IMX8ULP_CLK_HIFI_SEL>, <&cgc2 IMX8ULP_CLK_HIFI= _DIVCORE>; + assigned-clock-parents =3D <&cgc2 IMX8ULP_CLK_PLL4_PFD0>; + assigned-clock-rates =3D <0>, <475200000>; + memory-region =3D <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, + <&dsp_vdev0vring1>, <&dsp_reserved>; + status =3D "okay"; +}; + &flexspi2 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&pinctrl_flexspi2_ptd>; @@ -321,6 +351,10 @@ &mu { status =3D "okay"; }; =20 +&mu3 { + status =3D "okay"; +}; + &iomuxc1 { pinctrl_enet: enetgrp { fsl,pins =3D < --=20 2.34.1